US2003030078A1PendingUtilityA1

MOS transistor having aluminum nitrade gate structure and method of manufacturing same

41
Priority: Jan 26, 1999Filed: Oct 7, 2002Published: Feb 13, 2003
Est. expiryJan 26, 2019(expired)· nominal 20-yr term from priority
Inventors:Michael James ManfraLoren N. PfeifferKenneth William WestYiu-Huen Wong
H10P 14/6516H10P 14/6349H10P 14/6332H10D 64/01344H10D 64/01342H10D 64/0134H10P 14/69391H10D 64/693H10D 1/692C23C 14/5873C23C 14/083C23C 14/5806
41
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Claims

Abstract

An MOS transistor comprising a substrate, a source, a drain, and a gate, wherein the gate comprises aluminum nitride. Aluminum nitride is epitaxially grown on the silicon substrate at a substrate temperature of about 600° C. and subsequently annealed at a substrate temperature of about 950° C.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . An MOS transistor comprising: 
 a substrate;    a source;    a drain; and    a gate, wherein the gate comprises aluminum nitride.    
     
     
         2 . The MOS transistor of  claim 1 , further comprising a substrate electrode, a source electrode, a drain electrode, and a gate electrode formed on the substrate, the source, the drain, and the gate, respectively.  
     
     
         3 . The MOS transistor of  claim 1 , wherein the gate is fabricated using an epitaxial growth technique.  
     
     
         4 . The MOS transistor of  claim 3 , wherein the epitaxial growth technique is molecular beam epitaxy.  
     
     
         5 . The MOS transistor of  claim 1 , wherein the substrate is a (111) silicon substrate.  
     
     
         6 . The MOS transistor of  claim 5 , wherein the aluminum nitride is α-phase hexagonal aluminum nitride.  
     
     
         7 . The MOS transistor of  claim 6 , wherein the is α-phase hexagonal aluminum nitride is epitaxially grown with a nominal 18% lattice mismatch to the (111) silicon substrate.  
     
     
         8 . The MOS transistor of  claim 1 , wherein the substrate is a (100) silicon substrate.  
     
     
         9 . The MOS transistor of  claim 8 , wherein the aluminum nitride is β-phase crystalline form of cubic aluminum nitride.  
     
     
         10 . The MOS transistor of  claim 9 , wherein the β-phase crystalline form of cubic aluminum nitride is epitaxially grown with a nominal 18% lattice mismatch to the (100) silicon substrate.  
     
     
         11 . The MOS transistor of  claim 8 , wherein the aluminum nitride is β-phase crystalline form of zincblend aluminum nitride.  
     
     
         12 . The MOS transistor of  claim 1 , wherein the substrate is a (110) silicon substrate.  
     
     
         13 . The MOS transistor of  claim 12 , wherein the aluminum nitride is β-phase crystalline form of cubic aluminum nitride.  
     
     
         14 . The MOS transistor of  claim 13 , wherein the β-phase crystalline form of cubic aluminum nitride is epitaxially grown with a nominal 18% lattice mismatch to the (110) silicon substrate.  
     
     
         15 . The MOS transistor of  claim 12 , wherein the aluminum nitride is β-phase crystalline form of zincblend aluminum nitride.  
     
     
         16 . A method of making an MOS transistor comprising: 
 forming a source and drain in a substrate; and    forming a gate on the substrate, wherein the gate comprises aluminum nitride.    
     
     
         17 . The method of  claim 16 , further comprising forming a substrate electrode, a source electrode, a drain electrode, and a gate electrode on the substrate, the source, the drain, and the gate, respectively.  
     
     
         18 . The method of  claim 16 , wherein the gate is formed using an epitaxial growth technique.  
     
     
         19 . The method of  claim 18 , wherein the epitaxial growth technique is molecular beam epitaxy.  
     
     
         20 . The method of  claim 16 , wherein the substrate is a (111) silicon substrate.  
     
     
         21 . The method of  claim 20 , wherein the aluminum nitride is α-phase hexagonal aluminum nitride.  
     
     
         22 . The method of  claim 21 , wherein the α-phase hexagonal aluminum nitride is epitaxially grown with a nominal 18% lattice mismatch to the (111) silicon substrate.  
     
     
         23 . The method of  claim 16 , wherein the substrate is a (100) silicon substrate.  
     
     
         24 . The method of  claim 23 , wherein the aluminum nitride is β-phase crystalline form of cubic aluminum nitride.  
     
     
         25 . The method of  claim 24 , wherein the β-phase crystalline form of cubic aluminum nitride is epitaxially grown with a nominal 18% lattice mismatch to the (100) silicon substrate.  
     
     
         26 . The method of  claim 23 , wherein the aluminum nitride is β-phase crystalline form of zincblend aluminum nitride.  
     
     
         27 . The method of  claim 16 , wherein the substrate is a (110) silicon substrate.  
     
     
         28 . The method of  claim 27 , wherein the aluminum nitride is β-phase crystalline form of cubic aluminum nitride.  
     
     
         29 . The method of  claim 28 , wherein the β-phase crystalline form of cubic aluminum nitride is epitaxially grown with a nominal 18% lattice mismatch to the (110) silicon substrate.  
     
     
         30 . The method of  claim 27 , wherein the aluminum nitride is β-phase crystalline form of zincblend aluminum nitride.  
     
     
         31 . A method of forming an aluminum nitride film on a silicon substrate comprising: 
 epitaxially growing aluminum nitride on the silicon substrate at a substrate temperature of about 600° C.; and    subsequently annealing the substrate and epitaxially grown aluminum nitride at a substrate temperature of about 950° C.    
     
     
         32 . The method of  claim 31 , wherein the annealing is performed for 10 minutes.  
     
     
         33 . The method of  claim 31 , wherein the aluminum nitride is epitaxially grown at a rate of about 0.1 monolayer per second.  
     
     
         34 . The method of  claim 31 , wherein the aluminum nitride file is 10-100 Å thick.  
     
     
         35 . The method of  claim 31 , wherein the aluminum nitride is grown by molecular beam epitaxy.  
     
     
         36 . The method of  claim 31 , wherein the substrate is a (111) silicon substrate.  
     
     
         37 . The method of  claim 36 , wherein the aluminum nitride is α-phase hexagonal aluminum nitride.  
     
     
         38 . The method of  claim 37 , wherein the α-phase hexagonal aluminum nitride is epitaxially grown with a nominal 18% lattice mismatch to the (111) silicon substrate.  
     
     
         39 . The method of  claim 31 , wherein the substrate is a (100) silicon substrate.  
     
     
         40 . The method of  claim 39 , wherein the aluminum nitride is β-phase crystalline form of cubic aluminum nitride.  
     
     
         41 . The method of  claim 40 , wherein the β-phase crystalline form of cubic aluminum nitride is epitaxially grown with a nominal 18% lattice mismatch to the (100) silicon substrate.  
     
     
         42 . The method of  claim 39 , wherein the aluminum nitride is β-phase crystalline form of zincblend aluminum nitride.  
     
     
         43 . The method of  claim 31 , wherein the substrate is a (110) silicon substrate.  
     
     
         44 . The method of  claim 43 , wherein the aluminum nitride is β-phase crystalline form of cubic aluminum nitride.  
     
     
         45 . The method of  claim 44 , wherein the β-phrase crystalline form of cubic aluminum nitride is epitaxially grown with a nominal 18% lattice mismatch to the (110) silicon substrate.  
     
     
         46 . The method of  claim 43 , wherein the aluminum nitride is β-phase crystalline form of zincblend aluminum nitride.

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