Microcomputer

Abstract

A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

1 . A microcomputer comprising an integrated circuit device having a processor and memory in the form of RAM on the same integrated circuit device, and a plurality of communication links each including a register for storing a plurality of data bits and each arranged to provide a communication path for sole connection to a similar link of a further microcomputer whereby each microcomputer forms a building block for a network of microcomputers.  
     
     
         2 . A network of interconnected microcomputers each comprising a processor and memory in the form of RAM on a single integrated circuit device, each microcomputer having a plurality of communication links each interconnected by connecting means it with another microcomputer in the network, said links each forming part of a point to point connection which solely interconnects a respective pair of microcomputers and is not shared with any other microcomputer or memory, said links each including at least one register for holding a plurality of bits of data to be transmitted or received through the link.  
     
     
         3 . A microcomputer including on the same integrated circuit device memory in the form of RAM and a processor, said processor being arranged to execute a number of operations on data in response to a program consisting of a plurality of instructions for sequential execution by the processor, each instruction including a set of function bits which designate a required function to be executed by the processor, the function being one of a set of selectable functions, wherein: 
 (a) the microcomputer includes a plurality of communication links each arranged to provide a communication path for sole connection to a corresponding link of a further microcomputer, said communication links each including a register for storing a plurality of data bits for transmission through the communication link and temporary store means for receiving pointer values indicating the state of the link for use in synchronising message transmission through the link, and    (b) said processor includes: 
 (i) a plurality of registers and data transfer means for use in data transfers to and from said registers,  
 (ii) means for receiving each instruction and loading into one of the registers a value corresponding to the function bits of the instruction, and  
 (iii) control means for controlling said data transfer means and registers and arranged to respond to said function bits to cause the processor to operate in accordance with said function bits, the function set including one or more functions which cause said control means to load into the temporary store of the communication links pointer values for use in synchronising message transmission through the communication links.  
   
     
     
         4 . A microcomputer according to  claim 3  in which each link provides two unidirectional channels, one for outputs and one for inputs, each channel having a register for storing data bits and temporary store means for receiving pointer values.  
     
     
         5 . A microcomputer according to  claim 4  in which each communication link includes control logic arranged to cause transmission of data from a said register in an output channel of a communication link and to detect receipt of data in a said register of an input channel of a link, whereby communication between microcomputers may be effected concurrently through a plurality of links.  
     
     
         6 . A microcomputer according to  claim 5  in which said control logic is arranged to permit concurrent communication via the output and input channels of any one link.  
     
     
         7 . A microcomputer according to  claim 6  in which the control logic is arranged to permit data transfers between the registers of a pair of links independently of the processor, thereby permitting message transmission concurrently with process execution by the processor.  
     
     
         8 . A microcomputer according to  claim 7  in which said control logic includes means responsive to said pointer values in the temporary store means of each link and means for loading a pointer value into the said temporary store means for use in synchronising message transmission.  
     
     
         9 . A microcomputer according to  claim 8  in which said control logic includes means for generating signals for supply to the processor to indicate the state of the link.  
     
     
         10 . A microcomputer according to  claim 5  in which said control logic is arranged to respond to the state of registers in both input and output channels of each link and to cause transmission from an output channel of a data string and includes means for generating and detecting special values indicating the beginning and end of the string and means to cause an output channel to transmit an acknowledgment signal when the input channel of the same link has received the said special value representing the end of a data string.  
     
     
         11 . A microcomputer according to  claim 4  wherein the memory of the microcomputer provides one or more communication channels for message transmission between processes executed on the same microcomputer, each channel having at least one word location arranged to receive a pointer value for use in synchronising message transmission between the said processes, the said control means being arranged to respond to a selected function from the function set to locate a pointer value in said word location indicating the state of the channel for use in synchronising message transmission.  
     
     
         12 . A microcomputer according to  claim 11  in which the processor is arranged to use the same function, selected from the function set, for message synchronisation between processes on the same microcomputer as for processes on different microcomputers.  
     
     
         13 . A microcomputer according to  claim 4  in which said processor includes means for providing pointer values each indicating a respective process which is executed by the microcomputer, said control means being arranged to respond to functions in the function set to load into said register of the communication link a pointer indicating a particular process that is waiting to communicate through said channel together with means for loading into said register a special pointer value to indicate that no process is waiting to communicate through that channel.  
     
     
         14 . A network of interconnected microcomputers, each microcomputer being in accordance with  claim 3  and each microcomputer being connected to another microcomputer by connecting means between respective communication links, each connecting means between two microcomputers comprising two unidirectional point to point connections providing respectively input and output paths for each microcomputer.  
     
     
         15 . A network according to  claim 14  in which each link is arranged to transmit a message as a serial storing of bits and the said point to point connectrions provide a message path which is one bit wide.  
     
     
         16 . A method of communication of data between processes in an array of computers each comprising an integrated circuit device having a processor, memory and a plurality of communication links, comprising establishing dedicated connections between communication links of interconnected devices in the array whereby each connection is used solely for message transmission between the two devices which are interconnected by the connection, synchronising input and output message transmission through each link whereby message transmission may be effected concurrently through a plurality of links and connections without interrupting process execution by the processor of each microcomputer involved in the message transmission.  
     
     
         17 . A method according to  claim 16  in which a link of a microcomputer in said array is operated to transmit an output message through an output connection of a link concurrently with receipt of an input message through an input connection of the link.  
     
     
         18 . A method according to  claim 16  in which control logic of each link is operated to transmit data through a link as a serial storing of data bits and generates a first distinguishing bit pattern at the beginning of each message and a second different distinguishing bit pattern at the end of each message whereby the control logic of a receiving link may detect the beginning and end of each message.  
     
     
         19 . A method according to  claim 18  in which the control logic of a receiving link is arranged to generate an acknowledgement bit pattern for transmission to a transmitting link to indicate receipt of data of a predetermined bit length.  
     
     
         20 . In combination, 
 first and second integrated circuits each including a processor and multiple bit addressable memory;    a serial link for each of said integrated circuits, each link including an input portion and an output portion, each of said portions including a temporary storage means for storing data and information;    means coupling the input portion of said first integrated circuit to the output portion of said second integrated circuit only;    means coupling the output portion of said first integrated circuit to the input portion of said second integrated circuit only;    each of said serial links being coupled to communicate data and information to and from its corresponding processor or said addressable memory; 
 whereby data can be communicated from said first integrated circuit to said second integrated circuit and vice-versa directly and efficiently.  
   
     
     
         21 . A method for communication of data between processes in an array of computers, each comprising a single integrated circuit having a processor and multiple bit addressable memory, comprising: 
 establishing a communication link for permitting data to travel thereover between one of said single integrated circuits and one other device only;    storing predetermined indicia in a device associated with said link to indicate the status of data communication relative said communication link; and    responding to selected ones of sdid predetermined indicia to input or output data relative to one of the two devices involved in the communication.    
     
     
         22 . The method of  claim 21  wherein each of said links includes a “process” storage means and a data storage means, and wherein the method further includes a first indicium representative of a first of communication and a second indicium representative that data is ready to be inputted or outputted, the method including: 
 storing data in said data storage means corresponding to the outputting circuit and placing said second indicium in said “process” storage means;  
 sending data over said communication link from one of said data storage means to the other of said data storage means, and placing said first indicium in the “process” storage means of said one integrated circuit;  
 receiving data in the data storage means of the other device, and placing said second indicium in the “process” storage means thereof; and thereafter  
 fetching the data from said data storage means in said other device.  
 
     
     
         23 . The method of  claim 22  including placing a pointer in said “process” storage means and descheduling the corresponding process after a transmission of data by said integrated circuit; and scheduling the process corresponding to said pointer after receipt by said other circuit of said transmitted data.