Triple self-aligned split-gate non-volatile memory device

Abstract

A method for fabricating a triple self-aligned non-volatile memory device is disclosed. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.

What is claimed is:  
     
         1 . A method for fabricating a triple self-aligned non-volatile memory device on a substrate, comprising: 
 first forming isolation oxide over the substrate;    second forming a plurality of floating gates by first depositing and self-aligning the first polysilicon layer to the isolation oxide;    first defining a common source area on the substrate between said plurality of floating gates;    second depositing a second polysilicon layer over the common source area, and self-aligning the second polysilicon layer with respect to the isolation oxide;    third depositing a third polysilicon layer adjacent to the plurality of floating gates;    third forming a plurality of select gates by self-aligning the third polysilicon layer to the isolation oxide; and    second defining at least one drain area on the substrate.    
     
     
         2 . The method of  claim 1 , wherein the substrate includes silicon.  
     
     
         3 . The method of  claim 1 , wherein the non-volatile memory includes a flash memory device.  
     
     
         4 . The method of  claim 1 , wherein the isolation oxide includes a shallow trench isolation oxide.  
     
     
         5 . The method of  claim 1 , wherein the isolation oxide has a thickness in a range between about 60 and 120 angstroms.  
     
     
         6 . The method of  claim 1 , wherein the first polysilicon layer has a thickness in a range between about 1000 and 3000 angstroms.  
     
     
         7 . The method of  claim 1 , wherein said second forming a plurality of floating gates includes doping the first polysilicon layer with an impurity.  
     
     
         8 . The method of  claim 7 , wherein said impurity includes phosphorous ions.  
     
     
         9 . The method of  claim 7 , wherein the first polysilicon layer is ion implanted with said impurity at a concentration of about 1×10 19 /cm 3 .  
     
     
         10 . The method of  claim 1 , wherein said second forming a plurality of floating gates includes: 
 depositing a first oxide layer over the first polysilicon layer;    depositing a sacrificial polycrystalline layer over the first oxide layer;    depositing a second oxide layer on top of the sacrificial polycrystalline layer;    photomasking the second oxide layer; and    etching the second oxide layer and the sacrificial polycrystalline layer to remove an unmasked area.    
     
     
         11 . The method of  claim 10 , wherein said second forming a plurality of floating gates also includes: 
 depositing a nitride layer over the plurality of floating gates; and    plasma etching the nitride layer to form a spacer.    
     
     
         12 . The method of  claim 11 , wherein a thickness of the nitride layer ranges from about 300 to 800 angstroms.  
     
     
         13 . The method of  claim 11 , wherein said second forming a plurality of floating gates further includes: 
 etching the first polysilicon layer to define areas for the plurality of floating gates;    growing a thermal oxide layer over the defined areas for the plurality of floating gates;    depositing a third oxide layer over the thermal oxide layer; and    planar etching to produce said third oxide layer that is level with top surface of the sacrificial polycrystalline layer.    
     
     
         14 . The method of  claim 13 , wherein the thermal oxide layer has a thickness of about 60 to 120 angstroms.  
     
     
         15 . The method of  claim 1 , further comprising: 
 implanting ions at a flash cell channel area after said second forming a plurality of floating gates.    
     
     
         16 . The method of  claim 15 , wherein said ions includes boron ions.  
     
     
         17 . The method of  claim 15 , wherein an energy dose of said implanting ions ranges from about 150 to 200 KeV.  
     
     
         18 . The method of  claim 11 , wherein doping density of said implanting ions ranges from about 1×10 12 /cm 2  to 5×10 12 /cm 2 .  
     
     
         19 . The method of  claim 13 , further comprising: 
 forming a photoresistive masking layer over the third oxide layer and the sacrificial polycrystalline layer.    
     
     
         20 . The method of  claim 19 , further comprising: 
 implanting ions into the common source area using the photoresistive masking layer as a mask.    
     
     
         21 . The method of  claim 20 , wherein said implanting ions includes implanting arsenic ions.  
     
     
         22 . The method of  claim 21 , wherein an energy dose of said implanting arsenic ions ranges from about 50 to 100 KeV.  
     
     
         23 . The method of  claim 21 , wherein doping density of said implanting arsenic ions ranges from about 2×10 15 /cm 2  to 8×10 15 /cm 2 .  
     
     
         24 . The method of  claim 21 , further comprising: 
 implanting phosphorous ions.    
     
     
         25 . The method of  claim 24 , wherein an energy dose of said implanting phosphorous ions ranges from about 40 to 80 KeV.  
     
     
         26 . The method of  claim 24 , wherein doping density of said implanting arsenic ions ranges from about 1×10 15 /cm 2  to 6×10 15 /cm 2 .  
     
     
         27 . The method of  claim 1 , wherein said third polysilicon layer has thickness ranging from about 2000 to 4000 angstroms.  
     
     
         28 . The method of  claim 1 , further comprising: 
 doping said second polysilicon layer.    
     
     
         29 . The method of  claim 28 , further comprising: 
 planar etching said second polysilicon layer; and    growing oxide layer on top of said second polysilicon layer.    
     
     
         30 . The method of  claim 1 , wherein said third forming a plurality of select gates includes: 
 growing a first oxide layer on the substrate adjacent to said plurality of floating gates;    depositing a polycrystalline layer over the first oxide layer;    etching back said polycrystalline layer to form a polycrystalline spacer; and    depositing a second oxide layer over said polycrystalline layer.    
     
     
         31 . The method of  claim 30 , wherein said first oxide layer has a thickness ranging from about 120 to 300 angstroms.  
     
     
         32 . The method of  claim 30 , wherein said polycrystalline layer has a thickness of about 2000 to 4000 angstroms.  
     
     
         33 . The method of  claim 30 , further comprising: 
 depositing a Cobalt layer on top of the second oxide layer to form Cobalt salicide.    
     
     
         34 . A triple self-aligned non-volatile memory device, comprising: 
 an isolation oxide over a substrate;    a plurality of floating gates self-aligned to the isolation oxide, said plurality of floating gates including a first polysilicon layer;    a second polysilicon layer formed on top of a common source area in the substrate between said plurality of floating gates, said second polysilicon layer self-aligned to the isolation oxide;    a plurality of select gates adjacent to the plurality of floating gates, said plurality of select gates self-aligned to the isolation oxide; and    a contact formed to provide connection to a drain region.