Structure and fabrication method for capacitors integratible with vertical replacement gate transistors

Abstract

A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate. In an associated method of manufacture, a first device region, selected from the group consisting of the source region and a drain region of a field-effect transistor is formed on a semiconductor layer. A first field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers with a dielectric layer disposed therebetween, is also formed on the semiconductor layer. In another embodiment, the capacitor layers are formed within a trench or window formed in the semiconductor layer.

What is claimed is:  
     
         1 . A process for fabricating an integrated circuit structure comprising: 
 forming a first device region selected from the group consisting of a source region and a drain region of a semiconductor device in a semiconductor substrate;    forming a multilayer stack comprising at least three layers of material over the first device region in the semiconductor substrate, wherein the second layer is interposed between the first and the third layers, and wherein the first layer is adjacent the first device region;    forming a window in the at least three layers of material, wherein the window terminates at the first device region formed;    forming a doped semiconductor plug in the window, wherein the semiconductor plug has a first end and a second end, and wherein the first end is in contact with the first device region;    forming a second device region selected from the group consisting of a source region and a drain region in the second end of the semiconductor plug, wherein one of the first and second device regions is a source region and the other is a drain region.    removing the second layer, thereby exposing a portion of the semiconductor plug;    forming gate dielectric material on the exposed portion of the semiconductor plug;    forming a conductive layer comprising a horizontal segment and a vertical segment, wherein the vertical segment contacts the gate dielectric material to form a gate of a MOSFET device, and the horizontal segment forms a first capacitor plate;    forming a capacitor dielectric layer over the first capacitor plate; and    forming a second capacitor plate over the capacitor dielectric layer.    
     
     
         2 . The process of  claim 1  wherein the second layer is removed by etching in an etchant, characterized by a first layer etch rate, a second layer etch rate, and a third layer etch rate, and wherein the second layer etch rate is at least ten times faster than one of the first layer etch rate and the third layer etch rate.  
     
     
         3 . The process of  claim 1  wherein the semiconductor plug comprises a doped crystalline semiconductor material, and wherein the dopant is selected from the group consisting of n-type dopants and p-type dopants, and wherein the crystalline semiconductor material selected from the group consisting of silicon, silicon germanium, and silicon-germanium-carbon.  
     
     
         4 . The process of  claim 1  further comprising forming a layer of insulating material over either the first layer of material and the second layer of material, or both the first and second layers of material, wherein the layer of insulating material comprises an etch stop layer.  
     
     
         5 . The process of  claim 4  wherein the material of the first and the third layers comprises a doped insulating material, and wherein source and drain region extensions are formed within the semiconductor plug by the diffusion of dopants from the first and the third layers into the adjacent semiconductor plug material, and wherein the layer of insulating material comprises an offset spacer for controlling the extent of vertical diffusion of dopants from the first and the third layers.  
     
     
         6 . The process of  claim 1  wherein the substrate is selected from the group comprising silicon substrates and silicon-on-insulator substrates.  
     
     
         7 . The process of  claim 1  wherein the conductive material is selected from the group consisting of doped polycrystalline silicon, doped amorphous silicon, doped silicon germanium, doped silicon-germamum-carbon, metals and metal compounds  
     
     
         8 . The process of  claim 1  further comprising the steps of: 
 forming an insulating layer over the second capacitor plate; and  
 forming a window in the insulating layer for accessing the second capacitor plate.  
 
     
     
         9 . The process of  claim 8  wherein the insulating layer is selected from the group consisting of silicon nitride and silicon dioxide.  
     
     
         10 . The process of  claim 1  wherein the first and the second capacitor plates are formed of a material selected from the group comprising doped polysilicon, metal, and metal compounds.  
     
     
         11 . The process of  claim 1  wherein the capacitor dielectric layer is formed of material selected from the group comprising silicon dioxide and silicon nitride.  
     
     
         12 . The process of  claim 1  further comprising insulating the horizontal and the vertical segments of the conductive layer.  
     
     
         13 . The process of  claim 12  wherein an insulative trench insulates the horizontal and vertical segments of the conductive layer.  
     
     
         14 . A process for fabricating an integrated circuit structure comprising: 
 forming a first device region selected from the group consisting of a source region and a drain region of a semiconductor device in a semiconductor substrate;    forming a multilayer stack comprising at least three layers of material over the first device region in the semiconductor substrate wherein the second layer is interposed between the first and the third layers, and wherein the first layer is adjacent the first device;    forming a first and a second window in the at least three layers of material, wherein said first and second windows terminate at the first device region;    forming doped semiconductor material in the first window, thereby forming a doped semiconductor plug in the at least three layers of material, wherein the doped semiconductor plug has a first end and a second end, and wherein the first end is in contact with the first device region;    forming a second device region selected from the group consisting of a source region and a drain region in the second end of the doped semiconductor plug, wherein one of the first and second device regions is a source region and the other is a drain region;    removing the second layer, thereby exposing a portion of the doped semiconductor plug;    forming gate dielectric material on the exposed portion of the first semiconductor plug;    forming a gate in contact with the gate dielectric material;    forming a first conductive layer in the second window;    forming a first dielectric layer overlying the first conductive layer in the second window; and    forming a second conductive layer over the first dielectric layer in the second window, such that the first conductive layer, the first dielectric layer and the second conductive layer form a capacitor.    
     
     
         15 . The process of  claim 14  wherein the second layer is removed by etching in an etchant, characterized by a first layer etch rate, a second layer etch rate, and a third layer etch rate, and wherein the second layer etch rate is at least ten times faster than one of the first layer etch rate and the third layer etch rate.  
     
     
         16 . The process of  claim 15  wherein the etchant is selected from the group consisting of isotropic wet etchants and isotropic dry etchants.  
     
     
         17 . The process of  claim 14  wherein the material of the first layer and the third layer is an electrically insulating material is selected from the group consisting of silicon nitride, silicon dioxide, and doped silicon dioxide.  
     
     
         18 . The process of  claim 14  wherein the material of the first and the third layers comprises doped silicon dioxide, and wherein the process further comprises further doping the doped semiconductor plug with dopant from the first layer and the third layer to form doped extension regions in the doped semiconductor plug.  
     
     
         19 . The process of  claim 18  wherein the dopant type in the doped silicon dioxide is selected from the group consisting of n-type and p-type, and wherein the dopant type is opposite the dopant type in the doped semiconductor plug.  
     
     
         20 . The process of  claim 14  wherein the semiconductor plug material comprises a crystalline semiconductor material and is selected from the group consisting of silicon, silicon-germanium, and silicon-germanium-carbon.  
     
     
         21 . The process of  claim 14  further comprising forming an etch stop layer over either the first layer of material or the second layer of material, or over both the first and the second layers of material.  
     
     
         22 . The process of  claim 14  further comprising forming a diffusion barrier layer over the first device region before the at least three layers of material are formed thereover.  
     
     
         23 . The process of  claim 14  wherein the gate is formed from a material selected from the group consisting of doped polycrystalline silicon, doped amorphous silicon, doped polycrystalline silicon-germanium, doped amorphous silicon-germanium, doped polycrystalline silicon-germanium-carbon, doped amorphous silicon-germanium-carbon, metals and metal-containing compounds.  
     
     
         24 . The process of  claim 14  wherein the gate comprises a first and second segment, and wherein the first segment is formed in a region vacated by removal of the second layer in the area of the first window such that the first segment is adjacent the gate dielectric, and wherein the second segment is formed in the region vacated by removal of the second layer in the area of the second window such that the second segment is adjacent the first conductive layer in the second window, such that the gate dielectric material is electrically connected to a plate of the capacitor.  
     
     
         25 . The process of  claim 24  further comprising forming an insulative layer between the first and the second segments of the gate to isolate the gate dielectric material from the capacitor.  
     
     
         26 . The process of  claim 14  wherein the first and second conductive layers formed in the second window are formed from a material selected from the group consisting of doped polycrystalline silicon, doped amorphous silicon, doped polycrystalline silicon-germanium, doped amorphous silicon-germanium, doped polycrystalline silicon-germanium-carbon, doped a morphous silicon-germanium-carbon, metals and metal containing compounds.  
     
     
         27 . The process of  claim 14  wherein the first dielectric layer comprises material selected from the group consisting of silicon dioxide and silicon nitride.  
     
     
         28 . An integrated circuit structure comprising: 
 a semiconductor layer having a major surface formed along a plane;    a first doped region of a first conductivity type in a first area of the surface;    multiple layers over said first doped region, wherein said multiple layers have a window therein extending to said first doped region;    a second doped region of a second conductivity type in the window;    a third doped region of the first conductivity type over said second doped region;    a gate oxide adjacent said second doped region;    a first conductive layer comprising first and second segments, wherein said first segment is adjacent said gate oxide, and wherein said second segment extends to a second area of the surface;    a first dielectric layer over said second segment; and    a second conductive layer over said first dielectric layer.    
     
     
         29 . The integrated circuit structure of  claim 28  wherein the first doped region is a first source/drain region of a MOSFET, the second doped region is a channel region of the said MOSFET, and the third doped region is a second source/drain region of said MOSFET.  
     
     
         30 . The integrated circuit structure of  claim 29  wherein the first segment of the conductive layer comprises a gate of the MOSFET and a bottom plate of a capacitor.  
     
     
         31 . The integrated circuit structure of  claim 28  further comprising an insulator interposed between the first and the second segments of the first conductive layer so as to electrically isolate the first and the second segments.  
     
     
         32 . The integrated circuit structure of  claim 31  wherein the insulator is selected from the group comprising silicon dioxide, silicon nitride and air.  
     
     
         33 . The integrated circuit structure of  claim 31  wherein the first conductive layer is selected from the group consisting of doped polycrystalline silicon, dope amorphous silicon, doped silicon-germanium, doped silicon-germanium-carbon, metals and metal compounds.  
     
     
         34 . The integrated circuit structure of  claim 28  wherein the material of the first dielectric layer is selected from among silicon dioxide and silicon nitride.  
     
     
         35 . The integrated circuit structure of  claim 28  further comprising a second dielectric layer over the second conductive layer, wherein the second dielectric layer includes at least one via therein for providing conductive access to at least one of the second segment and the second conductive layer.  
     
     
         36 . An integrated structure comprising: 
 a semiconductor layer having a major surface formed along a plane;    a first doped region of a first conductivity type in a first area of the surface;    multiple layers over said first doped region, wherein said multiple layers have a window therein extending to said first doped region;    a second doped region of a second conductivity type in the window;    a third doped region of the first conductivity type over said second doped region;    an oxide layer adjacent said second doped region;    a first portion of a first conductive layer in contact with said oxide layer;    within a second window in a second area of the surface; 
 a second portion of said first conductive layer relatively conformal with the interior surface of said second window;  
 a conformal dielectric layer over said second portion of said first conductive layer; and  
 a second conductive layer over said dielectric layer, such that said second conductive layer, said first dielectric layer and said second portion of said first conductive layer form a capacitor.  
   
     
     
         37 . The integrated circuit structure of  claim 36  wherein the first portion of the first conductive layer comprises a gate of the MOSFET and wherein the second portion of the first conductive layer comprises a capacitor plate.  
     
     
         38 . The integrated circuit structure of  claim 36  wherein the material of the first conductive layer is selected from the group consisting of doped polycrystalline silicon, dope amorphous silicon, doped silicon-germanium, doped silicon-germanium-carbon, metals and metal compounds.  
     
     
         39 . The integrated circuit structure of  claim 36  wherein the material comprising the dielectric layer is selected from among silicon dioxide and silicon nitride.  
     
     
         40 . The integrated circuit structure of  claim 36  further comprising an insulator material disposed between the first and the second portions of the first conductive layer.