US2003060037A1PendingUtilityA1

Method of manufacturing trench conductor line

34
Priority: Sep 27, 2001Filed: Sep 27, 2001Published: Mar 27, 2003
Est. expirySep 27, 2021(expired)· nominal 20-yr term from priority
Inventors:Joseph Wu
H10W 20/084H10W 20/062H10W 20/076
34
PatentIndex Score
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Cited by
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References
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Claims

Abstract

A method of manufacturing a trench conductor line. An etching stop layer, a dielectric layer and a polishing stop layer are sequentially formed over a substrate. The polishing stop layer and the dielectric layer are patterned to form a trench that exposes a portion of the etching stop layer. A conformal dielectric layer is formed over the polishing stop layer and the interior surface of the trench. A portion of the conformal dielectric layer is removed to expose the polishing stop layer and the etching stop layer within the trench. A conductive layer is formed over the polishing stop layer filling the trench. The conductive layer is planarized using the polishing stop layer as a polishing stop.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A method of manufacturing a trench conductor line, comprising the steps of 
 providing a substrate having an etching stop layer thereon;    forming a dielectric layer over the etching stop layer;    forming a polishing stop layer over the dielectric layer;    patterning the polishing stop layer and the dielectric layer to form a trench that exposes a portion of the etching stop layer;    forming a conformal dielectric layer over the polishing stop layer and the interior of the trench;    removing a portion of the conformal dielectric layer to expose the polishing stop layer and a portion of the etching stop layer within the trench,    forming a conductive layer over the polishing stop layer and filling the trench; and    planarizing the conductive layer using the polishing stop layer as a polishing stop.    
     
     
         2 . The method of  claim 1 , wherein the etching stop layer has an etching rate lower than the dielectric layer.  
     
     
         3 . The method of  claim 1 , wherein material forming the etching stop layer includes silicon nitride.  
     
     
         4 . The method of  claim 1 , wherein material forming the dielectric layer includes silicon oxide.  
     
     
         5 . The method of  claim 1 , wherein the polishing stop layer has a polishing rate lower than the conductive layer.  
     
     
         6 . The method of  claim 1 , wherein material forming the conductive layer includes tungsten.  
     
     
         7 . The method of  claim 1 , wherein material forming the polishing stop layer includes silicon nitride.  
     
     
         8 . The method of  claim 1 , wherein material forming the conformal dielectric layer is selected from a group consisting of silicon nitride and silicon oxynitride.  
     
     
         9 . A method of manufacturing a trench conductor line, comprising the steps of: 
 providing a trench having an etching stop layer thereon;    forming a dielectric layer over the etching stop layer;    forming a polishing stop layer over the dielectric layer;    patterning the polishing stop layer and the dielectric layer to form trench that exposes a portion of the etching stop layer;    forming a conductive layer over the polishing stop layer and filling the trench; and    planarizing the conductive layer using the polishing stop layer as a polishing stop.    
     
     
         10 . The method of  claim 9 , wherein the etching stop layer has an etching rate lower than the second dielectric layer.  
     
     
         11 . The method of  claim 9 , wherein material forming the etching stop layer includes silicon nitride.  
     
     
         12 . The method of  claim 9 , wherein material forming the second dielectric layer includes silicon oxide.  
     
     
         13 . The method of  claim 9 , wherein the polishing stop layer has a polishing rate lower than the conductive layer.  
     
     
         14 . The method of  claim 9 , wherein material forming the polishing stop layer includes silicon nitride.  
     
     
         15 . A method of manufacturing a dual damascene structure, comprising the steps of: 
 providing a substrate having a first conductive structure and a second conductive structure thereon;    forming a first dielectric layer over the substrate that covers the first conductive structures and the second conductive structures;    forming a etching stop layer, a second dielectric layer and a polishing stop layer over the first dielectric layer sequentially;    patterning the polishing stop layer, the second dielectric layer, the etching stop layer and the first dielectric layer to form a first via opening and a second via opening, wherein the first via opening exposes a portion of the first conductive structure and the second via opening exposes a portion of the substrate and is on one side of the second conductive structure;    patterning the polishing stop layer and the second dielectric layer to form a first trench and a second trench, wherein the first trench and the second trench expose the etching stop layer, and a first dual damascene opening is composed of the first trench and the first via opening and a second dual damascene opening is composed of the second trench and the second via opening;    forming a conformal dielectric layer over the polishing stop layer and the interior surface of the first and the second dual damascene opening;    removing a portion of the conformal dielectric layer to expose the polishing stop layer, the first conductive structure inside the first dual damascene opening and a portion of the substrate inside the second dual damascene opening;    forming a conductive layer over the polishing stop layer and filling the first dual damascene opening and the second dual damascene opening; and    planarizing the conductive layer using the polishing stop layer as a polishing stop.    
     
     
         16 . The method of  claim 15 , wherein the etching stop layer has an etching rate lower than the second dielectric layer.  
     
     
         17 . The method of  claim 15 , wherein material forming the etching stop layer includes silicon nitride.  
     
     
         18 . The method of  claim 15 , wherein material forming the second dielectric layer includes silicon oxide.  
     
     
         19 . The method of  claim 15 , wherein the polishing stop layer has a polishing rate lower than the conductive layer.  
     
     
         20 . The method of  claim 15 , wherein material forming the polishing stop layer includes silicon nitride.

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