Method and apparatus for providing test mode access to an instruction cache and microcode rom

Abstract

A method and apparatus for providing full accessibility to on-chip instruction cache and microcode ROM are described. A dummy tag and a dummy instruction are written into a cache tag array and an instruction array, respectively, during a test mode. The dummy tag is concatenated with a predetermined set number and a predetermined word address to form a dummy address having a dummy tag field, a set field and a word address field. An instruction fetch is invoked using the dummy address. The instruction cache is accessed with the dummy address, and a cache miss is forced to occur. The dummy tag field of the dummy address is written into the tag array at a row specified by the predetermined set number, and the dummy instruction is written into the instruction array at the same row. Execution of the dummy instruction is suppressed. A read operation is performed in a similar manner, except in that case an instruction cache hit is forced to occur to cause data to be read from the instruction cache. Execution of the data read from the cache is suppressed. Microcode ROM is also read by invoking a dummy instruction fetch. The dummy instruction fetch causes data to be retrieved from a predetermined address in the ROM. Execution of the retrieved data is suppressed.

What is claimed is:  
     
         1 . In a microprocessor including an instruction cache, the cache having a tag array and an instruction array, the arrays being divided into a plurality of rows, wherein each row is specified by a set number, and the instruction array includes at least one instruction word field, a method for writing test data into the tag array and the instruction array during a test mode, the test data including a dummy tag and a dummy instruction, the method comprising the steps of: 
 (1) concatenating the dummy tag with a predetermined set number and a predetermined word address to thereby form a dummy address having a dummy tag field, a set field and a word address field;    (2) invoking an instruction fetch using the dummy address as an instruction fetch address, the invoking step comprising the steps of: 
 accessing the instruction cache with the dummy address;  
 forcing an instruction cache miss to occur regardless of whether the dummy address hits the tag array;  
 writing the dummy tag field of the dummy address into the tag array at a row specified by the predetermined set number; and  
 writing the dummy instruction into the instruction array at the row specified by the set number; and  
   (3) suppressing execution of the dummy instruction.    
     
     
         2 . The method of  claim 1 , the step of writing the dummy instruction further comprising the step of suppressing an external memory access.  
     
     
         3 . The method of  claim 1 , wherein the microprocessor includes a procedure return stack, the method further comprising the steps of: 
 pushing a return address onto the procedure return stack;    pushing the dummy address and a first state bit onto the procedure return stack, wherein the first state bit indicates the test mode;    the step of invoking the instruction fetch further comprising the step of executing a procedure return instruction, wherein the steps of forcing a cache miss and suppressing execution of the dummy instruction are performed in response to the first state bit indicating the test mode.    
     
     
         4 . The method of  claim 3 , the step of popping the return address off the procedure ask to continue instruction fetching.  
     
     
         5 . The method of  claim 1 , further comprising the step of repeating steps (1), (2) and (3) to write dummy instructions into a plurality of instruction word fields of at least one row of the cache.  
     
     
         6 . The method of  claim 1 , the cache being an N-way set-associative cache, the method further comprising the steps of writing the dummy tag field of the dummy address into a predetermined way of the tag array, and writing the dummy instruction into a predetermined way of the instruction array.  
     
     
         7 . The method of  claim 1 , the cache being an N-way set-associative cache, the method further comprising the step of repeating steps (1), (2) and (3) to write dummy instructions into a plurality of instruction word fields in a plurality of ways in at least one row of the cache.  
     
     
         8 . The method of  claim 1 , the microprocessor further comprising programming logic, wherein the method is implemented through execution of the programming logic.  
     
     
         9 . The method of  claim 8 , wherein execution of the programming logic is invoked by a BIST routine.  
     
     
         10 . The method of  claim 8 , wherein execution of the programming logic is invoked by a user-input instruction.  
     
     
         11 . The method and apparatus of  claim 8 , wherein execution of the programming logic is invoked by an event handler.  
     
     
         12 . The method of  claim 1 , further comprising the step of writing a dummy tag valid bit into the tag array at the row specified by the predetermined set number, wherein the dummy tag valid bit corresponds to the dummy tag.  
     
     
         13 . The method of  claim 1 , further comprising the step of writing a dummy word valid bit into the instruction array at the row specified by the set number, wherein the dummy word valid bit corresponds to the dummy instruction.  
     
     
         14 . The method of  claim 1 , further comprising the step of writing a dummy LRU bit into the tag array at the row specified by the set number.  
     
     
         15 . In a microprocessor including an instruction cache, the cache having a tag array and an instruction array, the arrays being divided into a plurality of rows, wherein each row is specified by a set number, and the instruction array includes at least one instruction word field, an apparatus for writing test data into the tag array and the instruction array during a test mode, the test data including a dummy tag and a dummy instruction, the apparatus comprising: 
 first programming logic for concatenating the dummy tag with a predetermined set number and a predetermined word address to thereby form a dummy address having a dummy tag field, a set field and a word address field;    hit logic for forcing an instruction cache miss to occur regardless of whether the dummy address hits the tag array, the bit logic forcing the cache miss when test data is to be written during the test mode,    wherein the tag array stores the dummy tag field of the dummy address at a row specified by the predetermined set number; and    a bus controller for suppressing an external memory access in response to the forced cache miss and instead providing the dummy instruction to the instruction array from an instruction test storage element,    wherein the instruction array stores the dummy instruction at a row specified by the predetermined set number.    
     
     
         16 . The apparatus of  claim 15 , wherein the microprocessor includes a procedure return stack, the apparatus further comprising second programming logic for: 
 pushing a return address onto the procedure return stack;    pushing the dummy address and a first state bit onto the procedure return stack, wherein the first state bit indicates the test mode; and    executing a procedure return instruction to invoke a dummy instruction fetch using the dummy address,    wherein, in response to the first state bit indicating the test mode when test data is to be written, the hit logic forces a cache miss, and, in response to the first state bit indicating the test mode, the microprocessor suppresses execution of the dummy instruction.    
     
     
         17 . The apparatus of  claim 15 , wherein the first programming logic is invoked by a BIST routine.  
     
     
         18 . The apparatus of  claim 15 , wherein the first programming logic is invoked by a user-input instruction.  
     
     
         19 . The apparatus of  claim 15 , wherein the first programming logic is invoked by an event handler.  
     
     
         20 . The apparatus of  claim 16 , wherein the first programming logic and the second programming logic are invoked by a BIST routine.  
     
     
         21 . The apparatus of  claim 16 , wherein the first programming logic and the second programming logic are invoked by a user-input instruction.  
     
     
         22 . The apparatus of  claim 16 , wherein the first programming logic and the second programming logic are invoked by an event hander.  
     
     
         23 . The apparatus of  claim 15 , further comprising logic for writing a dummy tag valid bit into the tag array at the row specified by the predetermined set number, wherein the dummy tag valid bit corresponds to the dummy tag.  
     
     
         24 . The apparatus of  claim 15 , further comprising logic for writing a dummy word valid bit into the instruction array at the row specified by the set number, wherein the dummy word valid bit corresponds to the dummy instruction.  
     
     
         25 . The apparatus of  claim 15 , further comprising logic for writing a dummy LRU bit into the tag array at the row specified by the set number.  
     
     
         26  In a microprocessor including an instruction cache, the cache having a tag array and an instruction array, the arrays being divided into a plurality of rows, wherein each row is specified by a set number, and the instruction array includes at least one instruction word field, a method for reading data from the cache during a test mode, the method comprising the steps of: 
 (1) concatenating a dummy tag with a predetermined set number and a predetermined word address to thereby form a dummy address having a dummy tag field, a set field and a word address field; and  
 (2) invoking an instruction fetch using the dummy address as an instruction fetch address, the invoking step comprising the steps of: 
 accessing the instruction cache with the dummy address;  
 forcing an instruction cache hit to occur regardless of whether the dummy address hits the tag array;  
 reading data from the cache at a row specified by the predetermined set number; and  
 
 (3) suppressing execution of the data.  
 
     
     
         27 . The method of  claim 26 , the reading step comprising the step of reading the tag array at a row specified by the predetermined set number.  
     
     
         28 . The method of  claim 26 , the reading step comprising the step of reading an instruction from the instruction array at a row specified by the predetermined set number.  
     
     
         29 . The method of  claim 26 , wherein the microprocessor includes a procedure return stack, the method further comprising the steps of: 
 pushing a return address onto the procedure return stack;    pushing the dummy address and a first state bit onto the procedure return stack, wherein the first state bit indicates the test mode;    the step of invoking the instruction fetch further comprising the step of executing a procedure return instruction, wherein the step of suppressing execution of the data is performed in response to the first state bit indicating the test mode.    
     
     
         30 . The method of  claim 29 , further comprising the step of popping the return address off the procedure return stack to continue instruction fetching.  
     
     
         31 . The method of  claim 27 , wherein the cache is an N-way set-associative cache, the method further comprising the step of reading a tag from a predetermined way of the tag array.  
     
     
         32 . The method of  claim 31 , the step of forcing a hit including the step of indicating a hit for the predetermined way.  
     
     
         33 . The method of  claim 28 , wherein the cache is an N-way set-associative cache, the method further comprising the step of reading an instruction word from a predetermined way of the instruction array.  
     
     
         34 . The method of  claim 33 , the step of forcing a hit including the step of indicating a hit for the predetermined way.  
     
     
         35 . The method of  claim 26 , further comprising the step of repeating steps (1), (2) and (3) to read data from a plurality of instruction word fields of at least one row of the cache.  
     
     
         36 . The method of  claim 26 , wherein the cache is an N-way set-associative cache, the method further comprising the step of repeating steps (1), (2) and (3) to read data from a plurality of instruction word fields of a plurality of ways of at least one row of the cache.  
     
     
         37 . The method of  claim 26 , wherein the cache is an N-way set-associative cache, the method further comprising the step of repeating steps (1), (2) and (3) to read data from a plurality of at least one row of the tag array.  
     
     
         38 . The method of  claim 26 , the microprocessor further comprising programming logic, wherein the method is implemented through execution of the programming logic.  
     
     
         39 . The method of  claim 38 , wherein execution of the programming logic is invoked by a BIST routine.  
     
     
         40 . The method of  claim 38 , wherein execution of the programming logic is invoked by a user-input instruction.  
     
     
         41 . The method and apparatus of  claim 38 , wherein execution of the programming logic is invoked by an event handler.  
     
     
         42 . The method of  claim 26 , further comprising the step of reading a tag valid bit from the tag array at the row specified by the predetermined set number, wherein the tag valid bit corresponds to the dummy tag.  
     
     
         43 . The method of  claim 26 , further comprising the step of reading a word valid bit from the instruction array at the row specified by the set number.  
     
     
         44 . The method of  claim 26 , further comprising the step of reading an LRU bit from the tag array at the row specified by the set number.  
     
     
         45 . In a microprocessor including an instruction cache, the cache having a tag array and an instruction array, the arrays being divided into a plurality of rows, wherein each row is specified by a set number, and the instruction array includes at least one instruction word field, an apparatus for reading data from the cache during a test mode, the apparatus comprising: 
 first programming logic for concatenating the dummy tag with a predetermined set number and a predetermined word address to thereby form a dummy address having a dummy tag field, a set field and a word address field;    hit logic for forcing an instruction cache hit to occur regardless of whether the dummy address hits the tag array, the hit logic forcing the cache hit when data is to be read during the test mode,    wherein the cache provides data from the row specified by the predetermined set number and the microprocessor suppresses execution of the data.    
     
     
         46 . The apparatus of  claim 45 , further comprising a data path multiplexer, coupled to the tag array and the instruction array, for selectively outputting either a tag from the tag array or an instruction word from the instruction array as the data read from the row specified by the predetermined set number.  
     
     
         47 . The apparatus of  claim 46 , wherein the data path multiplexer selectively outputs a tag valid bit along with the tag from the tag array.  
     
     
         48 . The apparatus of  claim 46 , wherein the data path multiplexer selectively outputs a word valid bit from the instruction array along with the tag from the tag array.  
     
     
         49 . The apparatus of  claim 46 , wherein the data path multiplexer selectively outputs an LRU bit from the tag array along with the tag from the tag array.  
     
     
         50 . The apparatus of  claim 46 , further comprising a cache control storage element for storing a data path control bit, wherein the data path control bit controls the output selection of the data path multiplexer.  
     
     
         51 . The apparatus of  claim 45 , wherein the cache is an N-way set-associative cache, and the hit logic forces a hit for a predetermined way.  
     
     
         52 . The apparatus of  claim 51 , further comprising a cache control storage element, wherein the predetermined way is indicated by at least one way bit stored in the cache control storage element.  
     
     
         53 . The apparatus of  claim 45 , wherein the microprocessor includes a procedure return stack, the apparatus further comprising second programming logic for: 
 pushing a return address onto the procedure return stack;    pushing the dummy address and a first state bit onto the procedure return stack, wherein the first state bit indicates the test mode; and    executing a procedure return instruction to invoke a dummy instruction fetch using the dummy address,    wherein, in response to the first state bit indicating the test mode when data is to be read, the hit logic forces a cache hit, and, in response to the first state bit indicating the test mode, the microprocessor suppresses execution of the data read from the cache.    
     
     
         54 . The apparatus of  claim 45 , wherein the first programming logic is invoked by a BIST routine.  
     
     
         55 . The apparatus of  claim 45 , wherein the first programming logic is invoked by a user-input instruction.  
     
     
         56 . The method and apparatus of  claim 45 , wherein execution of the programming logic is invoked by an event handler.  
     
     
         57 . The apparatus of  claim 53 , wherein the first programming logic and the second programming logic are invoked by a BIST routine.  
     
     
         58 . The apparatus of  claim 53 , wherein the first programming logic and the second programming logic are invoked by a user-input instruction.  
     
     
         59 . The apparatus of  claim 53 , wherein the first programming logic and the second programming logic are invoked by an event hander.  
     
     
         60 . In a microprocessor including a microcode ROM, a method for reading data from the microcode ROM during mode, the method comprising the steps of: 
 invoking a dummy instruction fetch using a predetermined address as an instruction fetch address, wherein the dummy instruction fetch causes data to be retrieved from the predetermined address in the ROM; and    suppressing execution of the retrieved data.    
     
     
         61 . The method of  claim 60 , wherein the microprocessor includes a procedure return stack, the method further comprising the steps of: 
 pushing a return address onto the procedure return stack;    pushing the predetermined address and a first state bit onto the procedure return stack, wherein the first state bit indicates the test mode;    the step of invoking the instruction fetch further comprising the step of executing a procedure return instruction, wherein the step of suppressing execution of the retrieved data is performed in response to the first state bit indicating the test mode.    
     
     
         62 . The method of  claim 61 , further comprising the step of popping the return address off the procedure returns to continue instruction fetching.  
     
     
         63 . The method of  claim 60 , the microcode ROM for storing programming logic, wherein the method is implemented through execution of the programming logic.  
     
     
         64 . The method of  claim 63 , wherein execution of the programming logic is invoked by a BIST routine.  
     
     
         65 . The method of  claim 63 , wherein execution of the programming logic is invoked by a user-input instruction.  
     
     
         66 . The method and apparatus of  claim 63 , wherein execution of the programming logic is invoked by an event handler.  
     
     
         67 . In a microprocessor including a microcode ROM, an apparatus for reading data from the ROM during a test mode, the apparatus comprising: 
 first programming logic for invoking a dummy instruction fetch using a predetermined address as an instruction fetch address, wherein the dummy instruction fetch causes data to be retrieved from the predetermined address of the ROM,    wherein the microprocessor suppresses execution of the retrieved data during the test mode.    
     
     
         68 . The apparatus of  claim 67 , wherein the microprocessor includes a procedure return stack, the apparatus further comprising second programming logic for: 
 pushing a return address onto the procedure return stack;    pushing the predetermined address and a first state bit onto the procedure return stack, wherein the first state bit indicates the test mode; and    executing a procedure return instruction to invoke the dummy instruction fetch using the predetermined address,    wherein, in response to the first state bit indicating the test mode, the microprocessor suppresses execution of the data retrieved from the ROM.    
     
     
         69 . The apparatus of  claim 67 , wherein the first programming logic is invoked by a BIST routine.  
     
     
         70 . The apparatus of  claim 67 , wherein the first programming logic is invoked by a user-input instruction.  
     
     
         71 . The method and apparatus of  claim 67 , wherein execution of the programming logic is invoked by an event handler.  
     
     
         72 . The apparatus of  claim 68 , wherein the first programming logic and the second programming logic are invoked by a BIST routine.  
     
     
         73 . The apparatus of  claim 68 , wherein the first programming logic and the second programming logic are invoked by a user-input instruction.  
     
     
         74 . The apparatus of  claim 68 , wherein the first programming logic and the second programming logic are invoked by an event hander.