Charge pump or other charge storage capacitor including PZT layer for combined use as encapsulation layer and dielectric layer of ferroelectric capacitor and a method for manufacturing the same

Abstract

A charge storage capacitor includes a bottom electrode, a dielectric layer formed on the bottom electrode, and a local interconnect electrode formed on the dielectric layer, wherein the dielectric layer is an encapsulation layer, and a ferroelectric memory cell includes the charge storage capacitor.

1 . A method for forming a capacitor, comprising the steps of: 
 forming a bottom electrode;    forming an encapsulation layer on the bottom electrode; and    forming a local interconnect electrode on the encapsulation layer.    
     
     
         2 . The method for forming a capacitor according to  claim 1 , wherein the encapsulation layer includes PZT.  
     
     
         3 . The method for forming a capacitor according to  claim 1 , wherein the encapsulation layer is formed at a temperature as high as 700° C.  
     
     
         4 . The method for forming a capacitor according to  claim 2 , wherein the encapsulation layer is formed with plasma damage to improve linear dielectric performance.  
     
     
         5 . The method for forming a capacitor according to  claim 1 , wherein the capacitor is a charge storage capacitor.  
     
     
         6 . The method for forming a capacitor according to  claim 1 , wherein the encapsulation layer includes Pb-based perovskite dielectrics, aluminum oxide, tantalum oxide, BaTiO 3 , or other dielectrics.  
     
     
         7 . The method for forming a capacitor according to  claim 1 , wherein a thickness of the encapsulation layer is in a range of between 30-200 nm.  
     
     
         8 . The method for forming a capacitor according to  claim 1 , wherein a thickness of the bottom electrode is about 100 nm.  
     
     
         9 . A method for forming an integrated circuit, comprising a charge storage capacitor and a ferroelectric memory cell including a data storage capacitor, comprising the steps of: 
 forming a bottom electrode of the charge storage capacitor and a bottom electrode of the data storage capacitor on an integrated circuit substrate;    forming a ferroelectric layer on the bottom electrode of the data storage capacitor;    forming a top electrode layer on the ferroelectric layer;    forming a first encapsulation layer on the bottom electrode of the charge storage capacitor and a second encapsulation layer on the bottom electrode of the data storage capacitor including the ferroelectric layer and the top electrode, wherein the first encapsulation layer and the second encapsulation are formed simultaneously; and    forming a first interlayer dielectric layer on the first encapsulation layer and a second interlayer dielectric layer on the second encapsulation layer,    wherein the first encapsulation layer is a dielectric layer of the charge storage capacitor.    
     
     
         10 . The method for forming an integrated circuit according to  claim 9 , wherein the first and second encapsulation layers comprise PZT.  
     
     
         11 . The method for forming an integrated circuit according to  claim 10 , wherein the first and second encapsulation layers are formed at a temperature as high as 700° C.  
     
     
         12 . The method for forming an integrated circuit according to  claim 10 , wherein the first and second encapsulation layers are formed with plasma damage to improve linear dielectric performance.  
     
     
         13 . The method for forming an integrated circuit according to  claim 9 , wherein the first and second encapsulation layers include Pb-based perovskite dielectrics, aluminum oxide, tantalum oxide, BaTiO 3 , or other dielectrics.  
     
     
         14 . The method for forming an integrated circuit according to  claim 9 , further comprising the steps of: 
 etching the first interlayer dielectric layer to form a first opening to expose the first encapsulation layer;    etching the second interlayer dielectric layer and the second encapsulation layer to form a second opening to expose the top electrode of the data storage capacitor; and    forming a first local interconnect electrode in the first opening and a second local interconnect electrode in the second opening.    
     
     
         15 . The method for forming an integrated circuit according to  claim 10 , wherein the first local interconnect electrode comprises part of the charge storage capacitor.  
     
     
         16 . A method for forming an integrated circuit comprising a capacitor, comprising the steps of: 
 forming a bottom electrode;    forming a ferroelectric layer on the bottom electrode;    forming a top electrode on the ferroelectric layer;    forming an encapsulation layer on the top electrode, wherein the encapsulation layer completely covers the top electrode; and    forming a local interconnect electrode on the encapsulation layer, wherein the ferroelectric layer includes PZT.    
     
     
         17 . The method for forming an integrated circuit according to  claim 16 , wherein the encapsulation layer includes Pb-based perovskite dielectrics, aluminum oxide, tantalum oxide, BaTiO 3 , or other dielectrics.  
     
     
         18 . The method for forming an integrated circuit according to  claim 16 , wherein the encapsulation layer includes PZT.  
     
     
         19 . The method for forming an integrated circuit according to  claim 18 , wherein the encapsulation layer is formed at a temperature as high as 700° C.  
     
     
         20 . The method for forming an integrated circuit according to  claim 18 , wherein the encapsulation layer is formed with plasma damage to improve linear dielectric performance.  
     
     
         21 . The method for forming an integrated circuit according to  claim 18 , wherein the encapsulation layer is formed with a lower Pb (lead) concentration than the ferroelectric layer.  
     
     
         22 . The method for forming an integrated circuit according to  claim 18 , wherein the encapsulation layer and the ferroelectric layer are formed with different compositions.  
     
     
         23 . The method for forming an integrated circuit according to  claim 22 , wherein the different compositions include different concentrations of Pb, Zr, and/or Ti.  
     
     
         24 . The method for forming an integrated circuit according to  claim 18 , wherein the encapsulation layer and the ferroelectric layer are formed with different dopant concentrations.  
     
     
         25 . The method for forming an integrated circuit according to  claim 16 , wherein the bottom electrode is electrically isolated.  
     
     
         26 . The method for forming an integrated circuit according to  claim 16 , wherein the top electrode is electrically isolated.  
     
     
         27 . The method for forming an integrated circuit according to  claim 16 , wherein the bottom electrode forms a first electrode of the capacitor, the ferroelectric layer and the encapsulation layer form a dielectric layer of the capacitor, and the local interconnect electrode forms a second electrode of the capacitor.  
     
     
         28 . The method for forming an integrated circuit according to  claim 27 , wherein the capacitor is a charge storage capacitor.  
     
     
         29 . The method for forming an integrated circuit according to  claim 16 , wherein the capacitor is a charge storage capacitor.  
     
     
         30 . The method for forming an integrated circuit according to  claim 17 , wherein the capacitor comprises part of a ferroelectric memory cell.  
     
     
         31 . The method for forming an integrated circuit according to  claim 17 , wherein the integrated circuit further comprises a ferroelectric memory cell.  
     
     
         32 . The method for forming an integrated circuit according to  claim 16 , wherein a thickness of the ferroelectric layer is in a range between 150-200 nm.  
     
     
         33 . A method for forming an integrated circuit, comprising a charge storage capacitor and a ferroelectric memory cell including a data storage capacitor, comprising the steps of: 
 forming a bottom electrode of the charge storage capacitor and a bottom electrode of the data storage capacitor on an integrated circuit substrate;    forming a first ferroelectric layer on the bottom electrode of the charge storage capacitor and a second ferroelectric layer on the bottom electrode of the data storage capacitor;    forming a first top electrode on the first ferroelectric layer and a second top electrode on the second ferroelectric layer;    forming a first encapsulation layer on the bottom electrode of the charge storage capacitor, including the first ferroelectric layer and the first top layer;    forming a second encapsulation layer on the bottom electrode of the data storage capacitor, including the second ferroelectric layer and the second top layer, wherein the first encapsulation layer and the second encapsulation are formed simultaneously;    forming a first interlayer dielectric layer on the first encapsulation layer and a second interlayer dielectric layer on the second encapsulation layer,    etching the first interlayer dielectric layer to form a first opening to expose the first encapsulation layer;    etching the second interlayer dielectric layer and the second encapsulation layer to form a second opening to expose the top electrode of the data storage capacitor; and    forming a first local interconnect electrode in the first opening and a second local interconnect electrode in the second opening,    wherein the first local interconnect electrode comprises part of the charge storage capacitor.    
     
     
         34 . The method for forming an integrated circuit according to  claim 33 , wherein the first and second encapsulation layers comprise PZT.  
     
     
         35 . The method for forming an integrated circuit according to  claim 34 , wherein the first and second encapsulation layers are formed at a temperature as high as 700° C.  
     
     
         36 . The method for forming an integrated circuit according to  claim 34 , wherein the first and second encapsulation layers are formed with plasma damage to improve linear dielectric performance.  
     
     
         37 . The method for forming an integrated circuit according to  claim 33 , wherein the first and second encapsulation layers include Pb-based perovskite dielectrics, aluminum oxide, tantalum oxide, BaTiO 3 , or other dielectrics.  
     
     
         38 . The method for forming an integrated circuit according to  claim 33 , wherein the bottom electrode is electrically isolated.  
     
     
         39 . The method for forming an integrated circuit according to  claim 33 , wherein the top electrode is electrically isolated.  
     
     
         40 . The method for forming an integrated circuit according to  claim 33 , wherein the bottom electrode forms a first electrode of the charge storage capacitor, the first ferroelectric layer and the first encapsulation layer form a dielectric layer of the charge storage capacitor, and the first local interconnect electrode forms a second electrode of the charge storage capacitor.  
     
     
         41 . The method for forming an integrated circuit according to  claim 33 , wherein the first top electrode forms a first electrode of the charge storage capacitor, the first encapsulation layer forms a dielectric layer of the charge storage capacitor, and the first local interconnect electrode forms a second electrode of the charge storage capacitor.  
     
     
         42 . A method for forming a capacitor, comprising the steps of: 
 forming a bottom electrode;    forming a ferroelectric layer on the bottom electrode;    forming an encapsulation layer on the ferroelectric layer; and    forming a local interconnect electrode on the encapsulation layer.    
     
     
         43 . The method for forming a capacitor according to  claim 42 , wherein the encapsulation layer includes PZT.  
     
     
         44 . The method for forming a capacitor according to  claim 43 , wherein the encapsulation layer is formed at a temperature as high as 700° C.  
     
     
         45 . The method for forming a capacitor according to  claim 43 , wherein the encapsulation layer is formed with plasma damage to improve linear dielectric performance.  
     
     
         46 . The method for forming a capacitor according to  claim 44 , wherein the ferroelectric layer and the encapsulation layer form a dielectric layer of the capacitor.  
     
     
         47 . The method for forming a capacitor according to  claim 44 , wherein the encapsulation layer includes Pb-based perovskite dielectrics, aluminum oxide, tantalum oxide, BaTiO 3 , or other dielectrics.  
     
     
         48 . The method for forming a capacitor according to  claim 42 , wherein the capacitor is a charge storage capacitor.  
     
     
         49 . The method for forming a capacitor according to  claim 42 , wherein the capacitor comprises part of a ferroelectric memory cell.  
     
     
         50 . The method for forming a capacitor according to  claim 42 , wherein the capacitor comprises part of an integrated circuit.  
     
     
         51 . A method for forming an integrated circuit, comprising a charge storage capacitor and a ferroelectric memory cell including a data storage capacitor, comprising the steps of: 
 forming a bottom electrode of the charge storage capacitor and a bottom electrode of the data storage capacitor on an integrated circuit substrate;    forming a first ferroelectric layer on the bottom electrode of the charge storage capacitor and a second ferroelectric layer on the bottom electrode of the data storage capacitor;    forming a top electrode layer on the first and second ferroelectric layers;    etching the top electrode layer to remove from the first ferroelectric layer and to form a top electrode of the data storage capacitor on the second ferroelectric layer;    forming a first encapsulation layer on the bottom electrode of the charge storage capacitor including the first encapsulation layer and a second encapsulation layer on the bottom electrode of the data storage capacitor including the second ferroelectric layer and the top electrode; and    forming a first interlayer dielectric layer on the first encapsulation layer and a second interlayer dielectric layer on the second encapsulation layer,    wherein the first encapsulation layer and the second encapsulation are formed simultaneously.    
     
     
         52 . The method for forming an integrated circuit according to  claim 51 , wherein the first and second encapsulation layers comprise PZT.  
     
     
         53 . The method for forming an integrated circuit according to  claim 51 , wherein the first and second encapsulation layers include Pb-based perovskite dielectrics, aluminum oxide, tantalum oxide, BaTiO 3 , or other dielectrics.  
     
     
         54 . The method for forming an integrated circuit according to  claim 51 , further comprising the steps of: 
 etching the first interlayer dielectric layer to form a first opening to expose the first encapsulation layer;    etching the second interlayer dielectric layer and the second encapsulation layer to form a second opening to expose the top electrode of the data storage capacitor; and    forming a first local interconnect electrode in the first opening and a second local interconnect electrode in the second opening.    
     
     
         55 . The method for forming an integrated circuit according to  claim 54 , wherein the first local interconnect electrode comprises part of the charge storage capacitor.  
     
     
         56 . The method for forming an integrated circuit according to  claim 51 , wherein the first ferroelectric layer and the first encapsulation layer form a dielectric layer of the charge storage capacitor.