Semiconductor storage

Abstract

A sense amplifier for amplifying the potential difference between paired bit lines has a first transistor having the drain thereof connected to a bit line BL and the gate thereof connected to a bit line/BL, a second transistor having the drain thereof connected to the bit line/BL and the gate thereof connected to the bit line BL, and a third transistor and a fourth transistor provided in association with the first and second transistors, an identical sense amplifier actuating signal being applied to the gates thereof.

What is claimed is:  
     
         1 . A semiconductor storage comprising: 
 a plurality of memory cells;    a pair of bit lines connected to said plural memory cells and which are formed on a semiconductor substrate;    a first impurity layer of the first conductive type connected to one of said pair of bit lines and which is formed in said semiconductor substrate;    a second impurity layer of the first conductive type connected to the other of said pair of bit lines and which is formed in said semiconductor substrate;    a third impurity layer of the first conductive type formed in said semiconductor substrate;    a fourth impurity layer of the first conductive type formed in said semiconductor substrate;    a fifth impurity layer of the first conductive type to which a predetermined potential is applied and which is formed in said semiconductor substrate;    a sixth impurity layer of the first conductive type to which said predetermined potential is applied and which is formed in said semiconductor substrate;    a first conductive layer formed over said semiconductor substrate between said first impurity layer and said third impurity layer and which is connected to the other of said pair of bit lines;    a second conductive layer which is formed over said semiconductor substrate between said second impurity layer and said fourth impurity layer and which is connected to one of said pair of bit lines;    a third conductive layer formed over said semiconductor substrate between said third impurity layer and said fifth impurity layer and to which a sense amplifier actuating signal is applied; and    a fourth conductive layer formed over said semiconductor substrate between said fourth impurity layer and said sixth impurity layer and to which said sense amplifier actuating signal is applied.    
     
     
         2 . A semiconductor storage according to  claim 1 , wherein said third impurity layer is formed to surround said first impurity layer, said first conductive layer is formed in a loop shape, said fourth impurity layer is formed to surround said second impurity layer, and said second conductive layer is formed in a loop shape.  
     
     
         3 . A semiconductor storage according to  claim 1 , wherein the length or resistance of said third impurity layer between said first conductive layer and said third conductive layer is substantially equal to the length or resistance of said fourth impurity layer between said second conductive layer and said fourth conductive layer.  
     
     
         4 . A semiconductor storage according to  claim 1 , wherein said third conductive layer and said fourth conductive layer are interconnected.  
     
     
         5 . A semiconductor storage according to  claim 1 , wherein a LOCOS oxide film is formed between said third impurity layer and said fourth impurity layer.  
     
     
         6 . A semiconductor storage according to  claim 1 , wherein said third impurity layer and said fourth impurity layer are formed as the same impurity layers.  
     
     
         7 . A semiconductor storage according to  claim 7 , wherein the resistance between one of said bit lines and said fifth impurity layer is substantially equal to the resistance between the other of said bit lines and said sixth impurity layer.  
     
     
         8 . A semiconductor storage comprising: 
 a plurality of memory cells;    a pair of bit lines connected to said plural memory cells and which are formed over a semiconductor substrate;    a first impurity layer of the first conductive type connected to one of said pair of bit lines and which is formed in said semiconductor substrate;    a second impurity layer of the first conductive type connected to the other of said pair of bit lines and which is formed in said semiconductor substrate;    a third impurity layer of the first conductive type formed in said semiconductor substrate;    a fourth impurity layer of the first conductive type to which a predetermined potential is applied and which is formed in said semiconductor substrate;    a fifth impurity layer of the first conductive type to which said predetermined potential is applied and which is formed in said semiconductor substrate;    a first conductive layer formed over said semiconductor substrate between said first impurity layer and said third impurity layer and which is connected to the other of said pair of bit lines;    a second conductive layer which is formed over said semiconductor substrate between said second impurity layer and said third impurity layer and which is connected to one of said pair of bit lines;    a third conductive layer formed over said semiconductor substrate between said third impurity layer and said fourth impurity layer and to which a sense amplifier actuating signal is applied; and    a fourth conductive layer formed over said semiconductor substrate between said third impurity layer and said fifth impurity layer and to which said sense amplifier actuating signal is applied.    
     
     
         9 . A semiconductor storage according to  claim 8 , wherein said third impurity layer is formed to surround said first and second impurity layers, and said first and second conductive layers are formed in a loop shape.  
     
     
         10 . A semiconductor storage according to  claim 8 , wherein the length or resistance of said third impurity layer between said first conductive layer and said third conductive layer is substantially equal to the length or resistance of said third impurity layer between said second conductive layer and said fourth conductive layer.  
     
     
         11 . A semiconductor storage according to  claim 8 , wherein said third conductive layer and said fourth conductive layer are interconnected.  
     
     
         12 . A semiconductor storage according to  claim 8 , wherein the resistance between one of said bit lines and said fourth impurity layer is substantially equal to the resistance between the other of said bit lines and said fifth impurity layer.  
     
     
         13 . A semiconductor storage comprising: 
 a plurality of memory cells;    a pair of bit lines connected to said plural memory cells:    a first transistor having a first electrode thereof connected to one of said pair of bit lines and a control electrode thereof connected the other of said pair of bit lines;    a second transistor having a first electrode thereof connected to the other of said pair of bit lines and a control electrode thereof connected one of said pair of bit lines;    a third transistor wherein a sense amplifier actuating signal is supplied to a control electrode thereof, a first electrode thereof is connected to a second electrode of said first transistor, and a predetermined potential is applied to a second electrode thereof; and    a fourth transistor wherein said sense amplifier actuating signal is supplied to a control electrode thereof, a first electrode thereof is connected to a second electrode of said second transistor, and said predetermined potential is applied to a second electrode thereof.    
     
     
         14 . A semiconductor storage according to  claim 13 , wherein the control electrodes of said third transistor and said fourth transistor are interconnected.  
     
     
         15 . A semiconductor storage according to  claim 13 , wherein the control electrodes of said first transistor and said second transistor are formed in a loop shape.  
     
     
         16 . A semiconductor storage according to  claim 13 , wherein the distance or resistance between the second electrode of said first transistor and the first electrode of said third transistor is substantially equal to the distance or resistance between the second electrode of said second transistor and the first electrode of said fourth transistor.  
     
     
         17 . A semiconductor storage according to  claim 13 , wherein the second electrode of said first transistor and the first electrode of said third transistor are formed by a common first impurity layer in said semiconductor substrate, the second electrode of said second transistor and the first electrode of said fourth transistor are formed by a common second impurity layer in said semiconductor substrate, and the length or resistance of said first impurity layer between the control electrode of said first transistor and the control electrode of said third transistor is equal to the length or resistance of said second impurity layer between the control electrode of said second transistor and the control electrode of said fourth transistor.  
     
     
         18 . A semiconductor storage according to  claim 13 , wherein the second electrode of said first transistor, the first electrode of said third transistor, the second electrode of said second transistor, and the first electrode of said fourth transistor are formed by a common impurity layer in said semiconductor substrate, and the length or resistance of said impurity layer between the control electrode of said first transistor and the control electrode of said third transistor is equal to the length or resistance of said impurity layer between the control electrode of said second transistor and the control electrode of said fourth transistor.