Channel adaptive equalization precoding system and method

Abstract

A system and method for delivering increased speed, security, and intelligence to wireline and wireless systems. The present invention includes a new generation Fast Circuit Switch (packet/circuit) Communication processors and platform which enables a new Internet Exchange Networking Processor Architecture at the edge and core of every communication system, for next generation Web Operating System or Environment (WOE) to operate on with emphasis of a non-local processor or networking processor with remote web computing capabilities.

What is claimed is:  
     
         1 . A method for reducing the interference occurring on a signal having inter-symbol interference (ISI) portion, the communications system including a first node, the first node comprising a first transmission unit and a first reception unit, the first transmission unit comprising a precoder, the first reception unit comprising an equalizer, the method comprising the steps of: 
 receiving a first data signal at said first node, said first data signal traversing from said second node to said first node along a first signal channel;    equalizing said first data signal;    generating a set of equalization coefficients corresponding to the equalization of said first data signal traversing said first signal channel;    generating a second data signal at said first node;    equalizing said second data signal using said set of equalization coefficients to equalize said second data signal, to generate a precoded equalized data signal; and    transmitting said precoded equalized data signal over a second signal channel.    
     
     
         2 . The method of  claim 1 , wherein said set of equalization coefficients corresponds to characteristics of the first signal channel and the second signal channel.  
     
     
         3 . The method of  claim 1 , wherein said first data signal has a precursor ISI portion and a post-cursor ISI portion and the step of equalizing said first data signal comprises the steps of: 
 receiving said first data signal, said first data signal having a precursor ISI portion and a post-cursor ISI portion;    performing an equalization operation on said first data signal to reduce the precursor ISI and to generate an ISI equalized sample signal;    combining said ISI equalized sample signal and a post-cursor cancellation signal to generate an equalized estimated sample signal;    generating a detected symbol signal representing a preliminary symbol value of said equalized estimated sample signal;    receiving said equalized estimated sample signal and said detected symbol signal for further reducing the precursor ISI portion of said first data signal; and    receiving said detected symbol signal for further reducing the post-cursor interference on said detected symbol signal to generate said post-cursor cancellation signal.    
     
     
         4 . The method of  claim 3 , wherein the step of receiving said equalized estimated sample signal and said detected symbol signal for further reducing the precursor ISI portion of said first data signal, comprises the steps of: 
 receiving said detected symbol signal;    determining the precursor ISI on said detected symbol signal to generate a precursor cancellation signal;    receiving said equalized estimated sample signal;    delaying said equalized estimated sample signal by a first amount;    outputting a delayed equalized estimated sample signal; and    combining said precursor cancellation signal and said delayed equalized estimated sample signal to generate a second output signal representing said first data signal having a reduced precursor ISI portion.    
     
     
         5 . The method of  claim 4 , further comprising the steps of: 
 receiving said data sample signal;    delaying said data sample signal by a second amount;    outputting a delayed data sample signal; and    performing an equalization operation on said delayed data sample signal to reduce precursor ISI interference and to generate a delayed equalized signal.    
     
     
         6 . The method of  claim 5 , further comprising the steps of: 
 receiving said second output signal;    generating a DPIC slicer output signal representing a preliminary value of said second output signal; and    reducing the post-cursor interference of said DPIC slicer output signal to generate a DPIC post-cursor cancellation signal.    
     
     
         7 . The method of  claim 6 , wherein said second output is generated by combining said DPIC post-cursor cancellation signal with said precursor cancellation signal, said delayed equalized estimated sample signal and said delayed equalized signal.  
     
     
         8 . A system for transmitting a target data signal over a signal channel, said target data signal having an inter-symbol interference (ISI) portion, the system comprising: 
 an equalizer, for receiving a data sample signal and for generating at least one set of coefficients corresponding to characteristics of said signal channel and for performing equalization operation on said data sample signal, to reduce the ISI portion;    a precoder, coupled to said equalizer, for receiving said at least one set of coefficients to equalize said target data signal and for generating a precoded equalized target data signal; and    a transmitter, for receiving said precoded equalized target data signal and for transmitting said precoded equalized target data signal over said signal channel.    
     
     
         9 . The system of  claim 8 , wherein said equalizer comprises a memory device to store said set of coefficients.  
     
     
         10 . The system of  claim 8 , wherein said data sample signal has a precursor inter-symbol interference (ISI) portion and a post-cursor ISI portion, said equalizer comprises: 
 a first precursor equalizer, for receiving said data sample signal and for performing an equalization operation on said data sample signal to reduce the precursor ISI and to generate an ISI equalized sample signal;    a summer, coupled to said first precursor equalizer, for combining said ISI equalized sample signal and a post-cursor cancellation signal to generate an equalized estimated sample signal;    a slicer, coupled to said summer to receive said equalized estimated sample signal, for generating a detected symbol signal representing a preliminary symbol value of said equalized estimated sample signal;    a precursor canceller, for receiving said equalized estimated sample signal and said detected symbol signal, for further reducing the precursor interference, said precursor canceller having: 
 a finite impulse response filter, for receiving said detected symbol signal and for determining the precursor ISI on said detected symbol signal to generate a precursor cancellation signal,  
 a first delay component to receive said equalized estimated sample signal, for delaying said equalized estimated sample signal by a first amount and to output a delayed equalized estimated sample signal, said first amount corresponding to a delay caused by said slicer and finite impulse response filter,  
 a DPIC summer to combine said precursor cancellation signal and said delayed equalized estimated sample signal to generate a second output signal representing said data sample signal having a reduced precursor interference portion; and  
   a first post-cursor canceller, for receiving said detected symbol signal, and for reducing the post-cursor interference on said detected symbol signal to generate said post-cursor cancellation signal.    
     
     
         11 . The system of  claim 10 , wherein said post-cursor canceller includes a plurality of taps having input coefficients.  
     
     
         12 . The system of  claim 11 , wherein said coefficients automatically adjust in response to the post-cursor interference on the data sample signal.  
     
     
         13 . The system of  claim 10 , wherein said first precursor equalizer includes a plurality of taps having input coefficients to reduce the pre-cursor interference.  
     
     
         14 . The system of  claim 10 , wherein said finite impulse response filter includes a plurality of taps having input coefficients to reduce the pre-cursor interference.  
     
     
         15 . The system of  claim 10 , wherein said first delay component aligns said equalized estimated sample signal and said slicer output signal.  
     
     
         16 . The system of  claim 10 , further comprising: 
 a second delay component, coupled to receive said data sample signal for delaying said data sample signal by a second amount and for outputting a delayed data sample signal; and    a second precursor equalizer, for receiving said delayed data sample signal and for performing an equalization operation on said delayed data sample signal to reduce precursor interference and to generate a delayed equalized signal;    wherein said DPIC summer receives said delayed precursor equalized output wherein said delayed equalized estimated sample signal represents said data sample signal having a reduced precursor interference portion.    
     
     
         17 . The system of  claim 16 , wherein said second amount corresponds to a delay caused by said first precursor equalizer, said summer, and said first delay component reduced by the delay caused by said second precursor equalizer.  
     
     
         18 . The system of  claim 16 , wherein said second precursor equalizer includes a plurality of taps having input coefficients to reduce the pre-cursor interference.  
     
     
         19 . The system of  claim 16 , further comprising: 
 a DPIC slicer, coupled to said DPIC summer to receive said second output signal, for generating a DPIC slicer output signal representing a preliminary value of said second output signal; and    a second post-cursor canceller, for receiving said DPIC slicer output signal, and for reducing the post-cursor interference of said DPIC slicer output signal to generate a DPIC post-cursor cancellation signal;    wherein said DPIC summer combines said DPIC post-cursor cancellation signal with said precursor cancellation signal, said delayed equalized estimated sample signal and said delayed equalized signal to generate said second output.    
     
     
         20 . The system of  claim 19 , wherein said second post-cursor canceller includes a plurality of taps having input coefficients.  
     
     
         21 . The system of  claim 20 , wherein said coefficients automatically adjust in response to the post-cursor interference on the data sample signal.