Silicon-based PT/PZT/PT sandwich structure and method for manufacturing the same

Abstract

A silicon based PT/PZT/PT sandwich structure is disclosed. A dielectric layer is formed over a semiconductor substrate. The dielectric layer preferably comprises a silicon dioxide layer. A first and the second conductive films are sequentially formed over the dielectric layer. A first ferroelectric film is formed over the first and second conductive films. A second ferroelectric film is formed over the first ferroelectric film. A third ferroelectric film is formed over the second ferroelectric film. The resulting structure is annealed. A third and fourth conductive films are sequentially formed over the third ferroelectric layer. The third and fourth conductive films are patterned.

What is claimed is:  
     
         1 . A PT/PZT/PT sandwich structure for integrated circuit device, the structure comprising: 
 a semiconductor substrate;    a dielectric layer formed over the substrate;    a first conductive film formed over the dielectric layer;    a second conductive film formed over the first conductive film;    a first ferroelectric film formed over the second conductive film;    a second ferroelectric film formed over the first ferroelectric film;    a third ferroelectric film formed over the second ferroelectric film, wherein the dielectric constant of the first and the third ferroelectric films is lower than the second ferroelectric film, wherein the material of the first and the third ferroelectric films are made of same material;    a third conductive film formed over the second ferroelectric film; and    a fourth conductive film formed over the third conductive film.    
     
     
         2 . The structure according to  claim 1 , wherein the first and the third ferroelectric films comprises a PT film, wherein the lead content in the PT film is within a range of 0.9-1.1% w/v.  
     
     
         3 . The structure according to  claim 1 , the thickness of the first and third ferroelectric films is within a range between 0.01 to 0.10 μm.  
     
     
         4 . The structure according to  claim 1 , wherein the second ferroelectric film is formed in between the first and the third ferroelectric films, wherein the second ferroelectric film comprises a PZT film, and the first, the third ferroelectric films comprises a PT film.  
     
     
         5 . The structure according to  claim 4 , wherein the composition of the PZT film comprises of Pb x (Zr y Ti 1−y )O 3  wherein x=0.9-1.1, y=0.4-0.6.  
     
     
         6 . The structure according to  claim 1 , wherein the thickness of the second ferroelectric film are within a range of 0.15 to 2.0 μm.  
     
     
         7 . The structure according to  claim 1 , wherein the first, the second and the third ferroelectric films is formed by performing a sol-gel process.  
     
     
         8 . The structure according to  claim 1 , wherein after the third ferroelectric layer is formed, an annealing process is performed.  
     
     
         9 . The structure according to  claim 8 , wherein the annealing step is carried out at a temperature of 650-700° C. for a duration of 30-45 minutes, wherein the first, the second and the third ferroelectric films are transformed from an amorphous form to a stable well crystallized perovskite form.  
     
     
         10 . The structure according to  claim 1 , wherein the first and the third conductive films comprises a Ti film, wherein the thickness of the first and the third conductive films is within a range of 1000-2000 Å.  
     
     
         11 . The structure according to  claim 1 , wherein the second and the fourth conductive films comprises a Pt film, wherein the thickness of the second and the fourth conductive films is within a range of 50-100 Å.  
     
     
         12 . A method for fabricating a PT/PZT/PT sandwich structure for fabricating a memory cell capacitor of integrated circuit device, the method comprising: 
 providing a semiconductor substrate;    forming a dielectric layer over the substrate;    forming a first conductive film over the dielectric layer;    forming a second conductive film over the first conductive film;    forming a first ferroelectric film over the second conductive film;    forming a second ferroelectric film over the first ferroelectric film;    forming a third ferroelectric film over the second ferroelectric film, wherein the dielectric constant of the first and the third ferroelectric films is lower than the second ferroelectric film, wherein the material of the first and the third ferroelectric films are made of same material;    forming a third conductive film over the third ferroelectric film; and    forming a fourth conductive film over the third conductive film.    
     
     
         13 . The method according to  claim 12 , wherein the first and the third ferroelectric films comprises a PT film, wherein the lead content in the PT film is within a range of 0.9-1.1% w/v.  
     
     
         14 . The method according to  claim 12 , the thickness of the first and third ferroelectric films is within a range between 0.01 to 0.10 μm.  
     
     
         15 . The method according to  claim 12 , wherein the second ferroelectric film is formed in between the first and the third ferroelectric films, wherein the second ferroelectric film comprises a PZT film, and the first, the third ferroelectric films comprises a PT film.  
     
     
         16 . The method according to  claim 15 , wherein the composition of the PZT film comprises of Pb x (Zr y Ti 1−y )O 3  wherein x=0.9-1.1, y=0.4-0.6.  
     
     
         17 . The method according to  claim 12 , wherein the thickness of the second ferroelectric film is within a range of 0.15 to 2.0 μm.  
     
     
         18 . The method according to  claim 12 , wherein the first, the second and the third ferroelectric films are formed by performing a sol-gel process.  
     
     
         19 . The method according to  claim 1 , wherein after the step of forming the third ferroelectric layer, an annealing process is performed.  
     
     
         20 . The method according to  claim 19 , wherein the annealing step is carried out at a temperature of 650-700° C. for a duration of 30-45 minutes, wherein the first, the second and the third ferroelectric films are transformed from an amorphous form to a stable well crystallized perovskite form.  
     
     
         21 . The method according to  claim 12 , wherein the first and the third conductive films comprises a Ti film, wherein the thickness of the first and the third conductive films is within a range of 1000-2000 Å.  
     
     
         22 . The method according to  claim 12 , wherein the second and the fourth conductive films comprises a Pt film, wherein the thickness of the second and the fourth conductive films is within a range of 50-100 Å.