Method and system for robust distributed circuit synthesis

Abstract

Based upon a circuit design, a system generates a plurality of seed circuits. An initial circuit constraint is used to generate a plurality of constraints sets, one for each seed circuit. The plurality of seed circuits and the corresponding constraint sets are distributed to a plurality of processors. In parallel, the processors execute a design software application to generate a plurality of candidate circuits based on the constraints and the seed circuits. The best candidate of the plurality of candidate circuits may be used for additional iterations in the design process.

What is claimed is:  
     
         1 . A method of generating a circuit design comprising the steps of: 
 (a) receiving functional specifications, including initial circuit constraints;    (b) generating a plurality of seed circuits, wherein each seed circuit is a copy of the functional specifications;    (c) generating a plurality of variant constraint sets based on the initial circuit constraints;    (d) distributing each seed circuit and one of the plurality of variant constraint sets to one of a plurality of processors;    (e) generating, in parallel, a plurality of candidate circuits based on the plurality of seed circuits and variant constraints; and    (f) outputting a best candidate circuit design representing gate-level design data and corresponding best candidate circuit constraints, wherein the best candidate circuit is the candidate circuit that most closely matches the initial circuit constraints.    
     
     
         2 . The method of  claim 1 , wherein generating a plurality of variant constraint sets based on the initial circuit constraints comprises: 
 generating a plurality of variant constraint sets based on the initial circuit constraints, such that each variant constraint set represents a portion of a constraint range that includes a maximum desired delay for the circuit design.    
     
     
         3 . The method of  claim 2 , wherein the step of generating a plurality of variant constraint sets comprises: 
 perturbing each of the variant constraint sets proportional to the maximum delay.    
     
     
         4 . The method of  claim 1 , further comprising: 
 (g) generating the plurality of seed circuits based on the best candidate circuit design;    (h) generating the plurality of variant constraint sets based on the corresponding best candidate circuit constraints; and    (i) repeating steps (d) through (f).    
     
     
         5 . The method of  claim 1 , wherein the step of generating a plurality of seed circuits comprises: 
 generating a plurality of seed circuits, wherein each seed circuit represents a subsection of the functional specifications.    
     
     
         6 . An apparatus for generating a circuit design comprising: 
 a memory storing program instructions, and    a processor configured according to the program instructions to perform the steps of: 
 (a) receiving functional specifications, including initial circuit constraints;  
 (b) generating a plurality of seed circuits, wherein each seed circuit is a copy of the functional specifications;  
 (c) generating a plurality of variant constraints based on the initial circuit constraints;  
 (d) distributing each seed circuit and one of the plurality of variant constraint sets to one of a plurality of processors;  
 (e) generating, in parallel, a plurality of candidate circuits based on the plurality of seed circuits and variant constraints; and  
 (f) outputting a best candidate circuit design representing gate-level design data and corresponding best candidate circuit constraints, wherein the best candidate circuit is the candidate circuit that most closely matches the initial circuit constraints.  
   
     
     
         7 . The apparatus of  claim 6 , wherein the processor configured to perform the step of generating a plurality of variant constraint sets is further configured to perform the substep of: 
 generating a plurality of variant constraint sets based on the initial circuit constraints, such that each variant constraint set represents a portion of a constraint range that includes a maximum desired delay for the circuit design.    
     
     
         8 . The apparatus of  claim 7 , wherein the processor configured to perform the step of generating a plurality of variant constraints is further configured to perform the substep of: 
 perturbing each of the plurality of initial circuit constraints proportional to the maximum delay.    
     
     
         9 . The apparatus of  claim 6 , wherein the processor is configured to use program instructions to perform the steps of: 
 (g) generating the plurality of seed circuits based on the best candidate circuit;    (h) generating the plurality of variant constraint sets based on the corresponding best candidate circuit constraints; and    (i) repeating steps (d) through (f).    
     
     
         10 . The apparatus of  claim 6 , wherein the processor configured to perform the step of generating a plurality of seed circuits is further configured to perform the substep of: 
 generating a plurality of seed circuits, wherein each seed circuit represents a subsection of the functional specifications.    
     
     
         11 . A computer-usable medium having computer-readable code embodied therein for generating a circuit design, the computer-usable medium comprising: 
 (a) a component configured to receive functional specifications, including initial circuit constraints;    (b) a component configured to generate a plurality of seed circuits, wherein each seed circuit is a copy of the functional specifications;    (c) a component configured to generate a plurality of variant constraint sets based on the initial circuit constraints;    (d) a component configured to distribute each seed circuit and one of the plurality of variant constraint sets to one of a plurality of processors;    (e) a component configured to generate, in parallel, a plurality of candidate circuits based on the plurality of seed circuits and variant constraints; and    (f) a component configured to output a best candidate circuit representing gate-level design data and best candidate circuit constraints, wherein the best candidate circuit is the candidate circuit that most closely matches the initial circuit constraints.    
     
     
         12 . The medium of  claim 11 , wherein the component configured to generate a plurality of variant constraint sets based on the initial circuit constraints comprises: 
 a component configured to generate a plurality of variant constraint sets based on the initial circuit constraints, such that each variant constraint set represents a portion of a constraint range that includes a maximum desired delay for the circuit design.    
     
     
         13 . The medium of  claim 12 , wherein the component configured to generate a plurality of variant constraints comprises: 
 a component configured to perturb each of the plurality of initial circuit constraints proportional to the maximum delay of the corresponding seed circuit.    
     
     
         14 . The medium of  claim 11 , further comprising: 
 (g) a component configured to generate the plurality of seed circuits based on the best candidate circuit;    (h) a component configured to generate the plurality of variant constraint sets based on the corresponding best candidate circuit constraints; and    (i) a component configured to repeat steps (d) through (f).    
     
     
         15 . The medium of  claim 11 , wherein the component configured to generate a plurality of seed circuits is further configured to: 
 generate a plurality of seed circuits, wherein each seed circuit represents a subsection of the functional specifications.    
     
     
         16 . A system for generating a circuit design comprising: 
 (a) means for receiving functional specifications, including initial circuit constraints;    (b) means for generating a plurality of seed circuits based on the functional specifications;    (c) means for generating a plurality of variant constraint sets based on the initial circuit constraints;    d) means for distributing each seed circuit and one of the plurality of variant constraint sets to one of a plurality of processors;    (e) means for generating, in parallel, a plurality of candidate circuits based on one of the plurality of seed circuits and variant constraints; and    (f) means for outputting a best candidate circuit representing gate-level design data and best candidate circuit constraints, wherein the best candidate circuit is the candidate circuit that most closely matches the initial circuit constraints.