High speed turbo codes decoder for 3G using pipelined SISO Log-Map decoders architecture

Abstract

The invention encompasses several improved Turbo Codes Decoder method and apparatus to provide a more suitable, practical and simpler method for implementation a Turbo Codes Decoder in ASIC or DSP codes. (1) Two pipelined Log-MAP decoders are used for iterative decoding of received data. (2) A Sliding Window of Block N data are used on the input Memory for pipeline operations. (3) The output block N data from the first decoder A are stored in the RAM memory A, and the second decoder B stores output data in the RAM memory B, such that in pipeline mode Decoder A decodes block N data from the RAM memory B while the Decoder B decodes block N data from the RAM memory A at the same clock cycle. (4) Log-MAP decoders are simpler to implement in ASIC and DSP codes with, only Adder circuits, and are low-power consumption. (5) Pipelined Log-MAP decoders architecture provides high speed data throughput, one output per clock cycle.

1 . An apparatus of turbo codes decoder used as a baseband processor subsystem for iterative decoding a plurality of sequences of received data R n  representative of coded data X n  generated by a turbo codes encoder from a source of original data u n  into decoded data Y n  comprising of: 
 (a) two pipelined SISO Log-MAP Decoders each decoding input data from the other output data in an iterative mode.    (b) the first SISO Log-MAP Decoder A having three inputs: R 0 , R 1  connecting from the two Input Memory modules  48   49 , and Z 1  feeding-back from the buffer Memory B module  45  output; the output of the Adder  231  of two input values R 0  and Z 1  is connected to Decoder A  42 ; and the first Decoder output is connected to a buffer Memory A module  43 .    (c) the second SISO Log-MAP Decoder B having two inputs: R 2  connecting from the Input Memory module  41 , and Z 2  connecting from the buffer Memory A module output; and the second Decoder output is connected to a buffer Memory B module  45 .    (d) a buffer Memory A module  43  storing decoded data from the first Log-MAP Decoder A  42 , feeding data to the second Log-MAP Decoder B  44 .    (e) a buffer Memory B module  45  storing decoded data from the second Log-MAP Decoder B  44 , feeding-back data to the first Log-MAP Decoder A  42 .    (f) an Adder  231  to produce a sum values of the two inputs R 0  and Z 1  output for the first Log-MAP Decoder A  42 .    (g) Three Input Buffer Memory modules  48   49   41  storing input soft decision received data, and feeding data to the two Log-MAP Decoders.    (h) a Control logic state machine  47  controlling the overall operations of the Turbo Codes Decoder.    (i) a hard-decoder logic  46  producing a final decision of either logic zero 0 or logic one 1 at the end of the iterations.    
     
     
         2 . The Decoder system of  claim 1 , wherein each Log-MAP decoder uses the logarithm maximum a posteriori probability algorithm. The Decoder system of  claim 1 , wherein each Log-MAP decoder uses the soft-input and soft-output (SISO) method maximum a posteriori probability algorithm. 
 The Decoder system of  claim 1 , wherein each Log-MAP decoder uses the Log Max approximation algorithm.    
     
     
         3 . The Decoder system of  claim 1 , wherein the two serially connected SISO Log-MAP Decoders each decoding input data from the other output data in pipeline mode to produce soft decoded data each clock cycle.  
     
     
         4 . The Decoder system of  claim 1 , wherein the Memory modules use dual-port memory RAM. 
 The Decoder system of  claim 1 , wherein the input buffer Interleaver Memory module uses an interleaver to generate the write-address sequences of the Memory core in write-mode. In read-mode, the memory core read-address are normal sequences.    
     
     
         5 . The Decoder system of  claim 1 , wherein a Sliding Window of Block N is used on the input buffer Memory so that each block N data is decoded at a time one block after another in a pipeline scheme. 
 The Decoder system of  claim 1 , wherein the a Sliding Window of Block N is used on the input buffer Memory in a continuous circular wrap-around scheme for pipeline operations.    
     
     
         6 . A method for iterative decoding a plurality of sequences of received data R n  representative of coded data X n  generated by a Turbo Codes Encoder from a source of original data u n  into decoded data Y n  comprising the steps of: 
 (a) coupling two pipelined Log-MAP decoders serially connected, having buffer Memory A and buffer Memory B for storing decoded output and providing feedback input for the decoders.    (b) applying feedback signal from the output of the buffer Memory B to the first decoder A, by adding the intrinsic values Z 1  with the received signal R 0  input, to generate a first decoded output XO 1 .    (c) applying the first decoded output to the buffer Memory A, and feeding the data with the received signal R 2  input into the second decoder B to generate a second decoded output XO 2 .    (d) applying the second decoded output XO 2  to the buffer Memory B and feeding back the data to the first decoder A.    (e) executing operations in both Log-MAP Decoders at the same time such that each decoder use the other's output as an input in iterative decoding.    (f) applying a Sliding Window of Block N on the input buffer Memory so that each block N data is decoded at a time one block after another in a pipeline scheme.    (g) applying an iterative decoding on each input data for L times until a desire soft decision is achieved and a hard decode output is generated.    
     
     
         7 . An apparatus of SISO Log-MAP Decoder for decoding a plurality of sequences of soft-input data SD 0  and SD 1  generated by a receiver to produce decoded soft-output data Y comprising of: 
 (a) a Branch Metric module computing the two soft-input data SD 0  and SD 1  into branch metric values for each branch in the trellis.    (b) a Branch Metric Memory module storing the branch metric values for each stage k=0 . . . N.    (c) a State Metric module computing state metric values for each state in the trellis using branch metric values. A State Metric Computing module calculates the probability A(k) of each state transition in forward recursion and the probability B(k) in backward recursion.    (d) an Add-Compare-Select (ACS) circuit to compute state metric values at each node in the Trellis.    (e) a State Metric Memory module storing state metric values for each stage k=0 . . . N.    (f) a Log-MAP module computing the soft decision output based on the branch metric values and state metric values using log maximum a posteriori probability algorithm.    (g) a Control Logic state machine module controlling the overall operations of the Log-MAP decoder.    
     
     
         8 . The Decoder system of  claim 7 , wherein the decoder uses the logarithm maximum a posteriori probability algorithm. 
 The Decoder system of  claim 7 , wherein each Log-MAP decoder uses the Log Max approximation algorithm.    The Decoder system of  claim 7 , wherein the decoder uses the soft-input and soft-output (SISO) method Log maximum a posteriori probability algorithm.    
     
     
         9 . The Decoder system of  claim 7 , wherein the decoder implements state-metric in forward recursion with Add-Compare-Select (ACS). 
 The Decoder system of  claim 7 , wherein the decoder implements state-metric in backward recursion with Add-Compare-Select (ACS).    
     
     
         10 . The Decoder system of  claim 7 , wherein the decoder uses an 8-states Trellis state transition diagram for 3GPP PCCC Turbo Codes. 
 The Decoder system of  claim 7 , wherein the decoder uses an 16-states Trellis state transition diagram for Superorthogonal Turbo Codes SOTC.    The Decoder system of  claim 7 , wherein the decoder uses an N-states trellis state transition diagram for higher order Superorthogonal Turbo Codes SOTC.    
     
     
         11 . The Decoder system of  claim 7 , wherein the the branch metric module uses a binary adder, a binary Subtracter, and two binary two-complementers logic. 
 The Decoder system of  claim 7 , wherein the the state metric module uses a binary adder, a comparator, a Mux selector logic.    The Decoder system of  claim 7 , wherein the the log-map module uses binary adders, binary maximum selectors logic.    The Decoder system of  claim 7 , wherein the the branch metric memory module uses dual-port memory RAM.    The Decoder system of  claim 7 , wherein the soft decoder module uses soft decision algorithm.    
     
     
         12 . A method for Log-Map decoding a plurality of sequences of received data SD 0  and SD 1  generated by a receiver to produce decoded soft-output data Y comprising the steps of: 
 (a) computing the branch metric for each input data in a block N data for the branches entering each state in the Trellis, then storing the results into the BM Memory.    (b) computing the forward recursion state metric with ACS for each data in BM Memory, for a block N data, for the each state in the Trellis, then storing the results into the SM Memory.    (c) computing the backward recursion state metric with ACS for each data in BM Memory, for a block N data, for the each state in the Trellis, then storing the accumulated results into the SM Memory.    (d) computing the Log-Map values from each data in BM Memory and SM Memory, for a block N data, for the each state in the Trellis.    (e) applying soft decision algorithm for each state and generate soft decoded outputs.    
     
     
         13 . An apparatus of an ACS (add-compare-select) for computing a plurality of sequences of sm 0 , bm 0 , sm 1 , bm 1  data to select max output data A comprising of: 
 (a) an Adder 0  to compute the sum of state metric sm 0  and branch metric bm 0  data,  
 (b) an Adder 1  to compute the sum of state metric sm 1  and branch metric bm 1  data,  
 (c) a Comparator to compares the two sums,  
 (d) and a Multiplexer selects the larger sum for the state s(k).  
 
     
     
         14 . An apparatus of Super Orthogonal Turbo Codes (SOTC) Decoder used as a baseband processor subsystem for iterative decoding a plurality of sequences of received Walsh code data RW i  and RW −   i  representative of Walsh coded data W i  and W −   j  generated by a Super Orthogonal Turbo Codes (SOTC) Encoder from a source of original data u n  into decoded data Y n  comprising of: 
 (a) two pipelined SISO Log-MAP Decoders each decoding input data from the other output data in an iterative mode.    (d) a buffer Memory A module storing decoded data from the first Log-MAP Decoder A, feeding data to the second Log-MAP Decoder B.    (e) a buffer Memory B module storing decoded data from the second Log-MAP Decoder B, feeding-back data to the first Log-MAP Decoder A.    (f) an Adder to produce a sum values of the two inputs RW i  and Z 1  output for the first Log-MAP Decoder A.    (g) The Input Buffer Memory modules storing input soft decision received data, and feeding data to the two Log-MAP Decoders.    (h) a Control logic state machine controlling the overall operations of the Turbo Codes Decoder.    (i) a hard-decoder logic producing a final decision of either logic zero 0 or logic one 1 at the end of the iterations.