Packaging substrate and manufacturing method thereof, integrated circuit device and manufacturing method thereof, and saw device

Abstract

A basic portion layer 21 of a substrate electrode 12 a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in the sintered substrate member is polished. On the polished basic portion layer 21, the plating layers 22, 23, are formed, so that surface roughness of the substrate electrode 12 a may be, for example, not larger than 0.1 μmRMS. Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.

What is claimed is:  
     
         1 . A method of manufacturing a packaging substrate on which an integrated circuit element is mounted, said integrated circuit element having an element substrate, a predetermined conductive pattern and a projecting electrode formed on said element substrate, said method comprising the steps of: 
 forming a basic portion layer of a substrate electrode on a substrate member, said substrate electrode being electrically and mechanically connected with said projecting electrode;    polishing a surface of said basic portion layer; and    forming a plating layer on the polished basic portion layer.    
     
     
         2 . A method of manufacturing a packaging substrate on which an integrated circuit element is mounted, said integrated circuit element having an element substrate, a predetermined conductive pattern and a projecting electrode formed on said element substrate, said method comprising the steps of: 
 forming a basic portion layer of a substrate electrode on a substrate member of ceramics, said substrate electrode being electrically and mechanically connected with said projecting electrode;    sintering said substrate member on which said basic portion layer has been formed;    polishing a surface of said basic portion layer on the sintered substrate member; and    forming a plating layer on the polished basic portion layer.    
     
     
         3 . A method of manufacturing a packaging substrate as claimed in  claim 1 , wherein surface roughness of said substrate electrode is not larger than 0.1 μmRMS after said plating layer has been formed.  
     
     
         4 . A method of manufacturing a packaging substrate as claimed in  claim 1 , wherein said surface of said basic portion layer is polished by barrel polishing method or lapping method.  
     
     
         5 . A method of manufacturing a packaging substrate as claimed in  claim 1 , wherein a surface layer of said plating layer is a gold plating layer.  
     
     
         6 . A method of manufacturing an integrated circuit device for use in combination with said method of manufacturing a packaging substrate as claimed in  claim 1 , said method of manufacturing an integrated circuit device comprising the steps of: 
 preparing a packaging substrate manufactured by said method of manufacturing a packaging substrate;    preparing an integrated circuit element having an element substrate on which a predetermined conductive pattern and a projecting electrode are formed;    mounting said integrated circuit element on said packaging substrate with said projecting electrode of said integrated circuit element being electrically and mechanically connected with said substrate electrode of said packaging substrate; and    sealing said integrated circuit element mounted on said packaging substrate.    
     
     
         7 . A method of manufacturing an integrated circuit device as claimed in  claim 6 , wherein said projecting electrode is composed of gold.  
     
     
         8 . A packaging substrate on which an integrated circuit element is mounted, 
 said integrated circuit element having an element substrate, a predetermined conductive pattern and a projecting electrode formed on said element substrate, comprising: 
 a substrate electrode which is formed on said packaging substrate and which is composed of a basic portion layer and a plating layer formed on said basic portion layer, said substrate electrode being electrically and mechanically connected with said projecting electrode; and  
 surface roughness of said substrate electrode is not larger than 0.1 μmRMS.  
   
     
     
         9 . A packaging substrate as claimed in  claim 8 , wherein a surface of said basic portion layer is subjected to polishing.  
     
     
         10 . A packaging substrate as claimed in  claim 8 , wherein said packaging substrate is made of ceramics.  
     
     
         11 . An integrated circuit device for use in combination with said packaging substrate as claimed in  claim 8 , comprising: 
 said packaging substrate;    an integrated circuit element mounted on said packaging substrate, a predetermined conductive pattern and a projecting electrode being formed on an element substrate of said integrated circuit element, said projecting electrode being electrically and mechanically connected with said substrate electrode of said packaging substrate; and    a sealing member for sealing said integrated circuit element mounted on said packaging substrate.    
     
     
         12 . An integrated circuit device as claimed in  claim 11 , wherein at least one of said surface layer of said plating layer and said projecting electrode is composed of gold.  
     
     
         13 . An integrated circuit device comprising: 
 an integrated circuit element having an element substrate on which a predetermined conductive pattern and an element electrode are formed;    a packaging substrate on which a substrate electrode is formed, said substrate electrode being consisting of a conductive material with a glass material is mixed in the conductive material, a film-coated layer of a glass material being formed circularly in a sealing member adhering area including a portion on said substrate electrode, said integrated circuit element being mounted on said packaging substrate with said substrate electrode being electrically connected with said element electrode; and    a sealing member for hermetically sealing said integrated circuit element, said sealing member being adhered on said packaging substrate through an adhesive positioned on said film-coated layer.    
     
     
         14 . An integrated circuit device as claimed in  claim 13 , wherein said adhesive is made of resin.  
     
     
         15 . An integrated circuit device as claimed in  claim 13 , wherein said packaging substrate is made of ceramics.  
     
     
         16 . An integrated circuit device as claimed in  claim 13 , wherein said packaging substrate is made of low temperature cofired ceramics (LTCC).  
     
     
         17 . An integrated circuit device as claimed in  claim 13 , wherein said substrate electrode comprises a basic portion layer in which a glass material is mixed and of which a portion is joined with said film-coated layer, and a plating layer formed on an area except said film-coated layer on said basic portion layer.  
     
     
         18 . An integrated circuit device as claimed in  claim 13 , wherein said integrated circuit element is an SAW element having a predetermined frequency band and a central frequency thereof, said integrated circuit device being an SAW device including said SAW element mounted on said packaging substrate.  
     
     
         19 . An integrated circuit device as claimed in  claim 13 , wherein two said SAW elements having central frequencies of bands different from each other are mounted on said packaging substrate.  
     
     
         20 . A packaging substrate having an element mounting surface on which an integrated circuit element is mounted, said integrated circuit element having an element substrate, a predetermined conductive pattern and a projecting electrode formed on said element substrate, said packaging substrate comprising: 
 an external connecting terminal which has a predetermined height and which is electrically connected with a mounting substrate; and    a supporting layer which has a thickness not smaller than said predetermined height of said external connecting terminal;    said external connecting terminal and said supporting layer being formed on a terminal forming surface positioned at a side opposite to said element mounting surface;    said supporting layer being formed at least in an area corresponding to a position where said integrated circuit element is mounted.    
     
     
         21 . An integrated circuit device for use in combination with said packaging substrate as claimed in  claim 20 , said integrated circuit device comprising: 
 said packaging substrate;    said integrated circuit element which has an element substrate, a predetermined conductive pattern and a projecting electrode formed on said element substrate and which is mounted on said element mounting surface; and    a sealing member for sealing said integrated circuit element.    
     
     
         22 . A method of manufacturing an integrated circuit device, said method comprising the steps of: 
 preparing an integrated circuit element which has an element substrate, a predetermined conductive pattern and a projecting electrode formed on said element substrate;    preparing a packaging substrate which has an external connecting terminal having a predetermined height and is electrically connected with a mounting substrate, and a supporting layer which has a thickness not smaller than said predetermined height of said external connecting terminal; said supporting layer being formed at least in an area corresponding to a position where said integrated circuit element is mounted;    bringing said supporting layer into contact with said stage upon setting said packaging substrate on said stage with said element mounting surface being directed to the outside; and    joining said integrated circuit element to said element mounting surface of said packaging substrate by applying ultrasonic wave vibration while pushing said integrated circuit element towards said supporting layer.    
     
     
         23 . A method of manufacturing an integrated circuit device as claimed in  claim 22 , wherein said supporting layer is insulative.  
     
     
         24 . A method of manufacturing an integrated circuit device, said method comprising the steps of: 
 preparing an integrated circuit element which has an element substrate, a predetermined conductive pattern and a projecting electrode formed on said element substrate;    preparing a packaging substrate which has an external connecting terminal electrically connected with a mounting substrate and formed on a terminal forming surface positioned at a side opposite to said element mounting surface;    preparing a stage having a supporting projection capable of being contact with at least an area corresponding to a position where said integrated circuit element is mounted except said external connecting terminal forming area on said terminal forming area;    setting said packaging substrate on said supporting projection of said stage with said element mounting surface being directed to the outside; and    joining said integrated circuit element to said element mounting surface of said packaging substrate by applying ultrasonic wave vibration while pushing said integrated circuit element towards said supporting projection.    
     
     
         25 . A method of manufacturing an integrated circuit device as claimed in  claim 22 , wherein said packaging substrate is made of resin.  
     
     
         26 . A method of manufacturing an integrated circuit device as claimed in  claim 22 , wherein said integrated circuit element is an SAW element having a predetermined frequency band and a central frequency thereof, said integrated circuit device being an SAW device including said SAW element mounted on said packaging substrate.  
     
     
         27 . A method of manufacturing an integrated circuit device as claimed in  claim 22 , wherein two said SAW elements having central frequencies of bands different from each other are mounted on said packaging substrate.  
     
     
         28 . A packaging substrate comprising: 
 an element mounting surface on which an integrated circuit element is mounted, said integrated circuit element having an element substrate, a predetermined conductive pattern and a plurality of bumps formed on said element substrate; and    a ratio between a total area of said a plurality of bumps and a mass of said integrated circuit element being not smaller than 0.0085 mm2/mg.    
     
     
         29 . An SAW device comprising: 
 an SAW element which has a piezo-electric substrate and at least one pair of resonators each of which has a shape of the teeth of a comb with being involved in each other;    a packaging substrate on which said SAW element is mounted through a plurality of bumps; and    a ratio between a total area of said a plurality of bumps formed on said SAW element and a mass of the SAW element being not smaller than 0.0085 mm2/mg.    
     
     
         30 . An SAW device as claimed in  claim 29 , wherein said a plurality of bumps are gold bumps.  
     
     
         31 . An SAW device as claimed in  claim 29 , wherein an electrode on which said a plurality of bumps are formed is composed of aluminum having a film thickness between 0.5 μm and 1.0 μm, both inclusive.  
     
     
         32 . An SAW device as claimed in  claim 29 , wherein said SAW device is a branching filter on which two said SAW elements having central frequencies of bands different from each other are mounted.