Digital signal processor with variable length instruction set

Abstract

A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions may, but are not required to, occur across memory word boundaries. Preferably, the variable length instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation (or operations) to be performed, thereby allowing multiple operations to be performed during each clock cycle. This reduces the total number of clock cycles necessary to perform a task.

1 . A method for operating a digital signal processor using variable length instructions, said variable length instructions having a set of instruction fragments each for requesting an operation, comprising the steps of: 
 a) reading previously processed data from a first register into a first processing unit during a first clock phase of a first clock cycle;    b) processing said previously processed data based on a first instruction fragment from the set of instruction fragments, and during said first clock cycle, yielding twice processed data;    c) processing new data based on a second instruction fragment from said set of instruction fragments, and during said first clock cycle, producing new processed data;    d) writing said new processed data into said first register during a second phase of said first clock cycle; and    e) writing said twice processed data into a second register during said second phase of said first clock cycle.    
     
     
         2 . The method as set forth in  claim 1  wherein step b) is performed by a first processing unit, and step c) is performed by a second processing unit.  
     
     
         3 . The method as set forth in  claim 1  further comprising the steps of: 
 reading instruction data containing said variable length instructions;  
 deterrnining a next instruction length;  
 decoding an amount of data in said instruction data equal to said next instruction length.  
 
     
     
         4 . A microprocessor comprising: 
 first processing unit;    second processing unit; and    register readably coupled to said first processing unit and said second processing unit.    
     
     
         5 . The microprocessor as set forth in  claim 4  further comprising: 
 a data bus coupled to said register; and  
 a data memory coupled to said data bus.  
 
     
     
         6 . The microprocessor as set forth in  claim 4  further comprising: 
 a second register coupled to said first processing unit, but not to said second processing unit;  
 a third register coupled to said second processing unit but not said first processing unit.  
 
     
     
         7 . A system for controlling a digital signal processor comprising: 
 a memory having an address space addressable at address words, each of said address words having a front edge word boundary and a back edge boundary,    a set of variable length instructions stored in said memory, each of said variable length instructions having a front edge instruction boundary and a back edge boundary, wherein 
 a first portion of said variable length instructions have front edge instruction boundaries which correspond to said front edge word boundaries or have back edge instruction boundaries which correspond to said back edge word boundaries, and  
 a second portion of said variable length instructions have front edge instruction boundaries which are different than said front edge word boundaries and have back edge instruction boundaries which are different than said back edge word boundaries.  
   
     
     
         8 . The microprocessor as set forth in  claim 4  further comprising: 
 multiplexer for coupling said first processing to said register in a first configuration, and for coupling said second processing unit to said register in a second configuration.  
 
     
     
         9 . The microprocessor as set forth in  claim 8  further comprising: 
 control system for configuring said multiplexer based on instruction data.  
 
     
     
         10 . The microprocessor of  claim 4  wherein said first processing unit is a multiply accumulator.