Copper plated PTH barrels and methods for fabricating

Abstract

A circuitized semiconductor substrate comprising a layer of dielectric material having holes therethrough, a catalyst seed layer lining the walls of the holes along the surface of the dielectric material, and a nickel layer in the openings and a layer of copper above the nickel layer, along with a method for its fabrication. The invention also provides copper-nickel laminate PTH barrels and methods for their fabrication.

What is claimed is:  
     
         1 . A circuitized printed wiring board comprising: 
 a dielectric substrate provided with a pattern of vias;    a first metallization layer located on the inner surface of said pattern of vias;    a layer of Ni deposited on said first layer; and    a layer of Cu plated on said Ni layer.    
     
     
         2 . The circuitized printed wiring board of  claim 1  wherein said dielectric substrate comprises epoxy resin optionally reinforced.  
     
     
         3 . The circuitized printed wiring board of  claim 1  wherein said first metallization layer is deposited from a palladium/tin colloidal suspension.  
     
     
         4 . The circuitized printed wiring board of  claim 1  wherein the layer of nickel is about 1 to about 5 microns thick.  
     
     
         5 . The printed wiring board of  claim 1  wherein the layer of nickel is about 2.5 to about 3.5 microns thick.  
     
     
         6 . The printed wiring board of  claim 1  wherein the layer of dielectric material has a roughened surface.  
     
     
         7 . A method for fabricating a circuitized printed wiring board comprising: 
 providing at least one layer of dielectric material;    providing a pattern of vias in said dielectric material;    depositing a catalyst seed layer on said layer of dielectric material;    depositing and patterning a photoresist layer on said seed layer;    depositing a layer of nickel on top of said catalyst seed layer; and    depositing a layer of copper plating over said layer of nickel.    
     
     
         8 . The method of  claim 7  wherein the layer of dielectric material comprises epoxy resin optionally reinforced.  
     
     
         9 . The method of  claim 7  wherein the catalyst seed layer is deposited from a palladium/tin colloidal suspension.  
     
     
         10 . The method of  claim 7  wherein the nickel layer is deposited to a thickness of about 1 to about 5 microns.  
     
     
         11 . The method of  claim 7  wherein the nickel layer is deposited to a thickness of about 2.5 to about 3.5 microns.  
     
     
         12 . The method of  claim 7  wherein the copper is deposited by electroless plating  
     
     
         13 . The method of  claim 7 , wherein electroless plating comprises: 
 providing a copper electroless plating bath;    providing a dielectric material having PTH holes plated with nickel; and    immersing said dielectric material in said electroless plating bath.    
     
     
         14 . The method of  claim 13  wherein said electroless plating bath comprises oxygen not lower than 1.5 ppm below saturation  
     
     
         15 . The method of  claim 13  wherein said electroless plating bath comprises oxygen not lower than 1.0 ppm below saturation.  
     
     
         16 . The method of  claim 13  wherein the pH of said electroless plating bath is adjusted to the range from about 11.5 to about 12.0.  
     
     
         17 . The method of  claim 13  wherein the pH of said electroless plating bath is adjusted to the range from about 11.7 to about 11.9.  
     
     
         18 . The method of  claim 13  wherein said electroless plating bath comprises cyanide ion comprises from about 5 to about 11 ppm., and more typically about 5 to about 8 ppm of cyanide ions  
     
     
         19 . The method of  claim 13  wherein said cyanide ion comprises from about 5 to about 8 ppm.  
     
     
         20 . The method of  claim 13  wherein the specific gravity of said electroless plating bath is within the range of 1.06 to 1.08  
     
     
         21 . The method of  claim 13  wherein the temperature of said electroless plating bath is maintained between about 70° C. and 80° C.  
     
     
         22 . The method of  claim 13  wherein the temperature of said electroless plating bath is maintained between about 72° C. and 75° C.  
     
     
         23 . A copper-nickel laminate via barrel obtained by the method of  claim 7 .  
     
     
         24 . A circuitized printed wiring board obtained by the method of  claim 7 .  
     
     
         25 . A circuitized printed wiring board comprising: 
 a dielectric substrate having a top surface, and a bottom surface, and at least one via, said at least one via having a via barrel surface and at least one via peripheral entry surface;    a first metallization layer deposited on said via barrel surface and said at least one via peripheral entry surface of said at least one via, said top surface, and said bottom surface of said dielectric substrate;    a second metallization layer deposited on said first metallization layer on said via barrel surface and said at least one via peripheral entry surface of said at least one via, and selectively deposited on said first metallization layer on said top surface and said bottom surface of said dielectric substrate; and    a third metallization layer deposited on said second metallization layer on said first metallization layer on said via barrel surface and said at least one via peripheral entry surface of said at least one via, and selectively deposited on said second metallization layer on said first metallization layer on said top surface and said bottom surface of said dielectric substrate.    
     
     
         26 . The circuitized printed wiring board of  claim 25 , wherein said first metallization layer is a catalytic seed layer.  
     
     
         27 . The circuitized printed wiring board of  claim 26 , wherein said catalytic seed layer is chosen from the group consisting of palladium and tin.  
     
     
         28 . The circuitized printed wiring board of  claim 26 , wherein said second metallization layer is chosen from the group consisting of Group VIII and Group IB transition metals.  
     
     
         29 . The circuitized printed wiring board of  claim 26 , wherein said third metallization layer is chosen from the group consisting of manganese, iron, cobalt, nickel, copper, palladium, platinum, silver, and gold.  
     
     
         30 . A method for fabricating a circuitized printed circuit wiring board comprising: 
 providing a substrate having a top surface and a bottom surface;    providing at least one via having a barrel surface and at least one via peripheral entry surface in said substrate;    depositing a catalyst seed layer on said via barrel surface and said at least one via peripheral entry surface of said at least one via, said top surface and said bottom surface of said substrate;    providing a resist layer on selected areas over said catalyst seed layer on said top surface and said bottom surface of said substrate;    depositing a first metallization layer over areas of catalyst seed layer not protected by said protective resist layer on said top surface and said bottom surface of said substrate, and said via barrel surface and said at least one via peripheral entry surface of said at least one via; and    depositing a second metallization layer over said first metallization layer.    
     
     
         31 . The method of  claim 30  wherein said step of depositing a catalyst seed layer further includes processing selected from the group consisting of colloidal suspension, ionic solution, and organometallic solution.  
     
     
         32 . The method of  claim 30  wherein said catalytic seed layer is palladium.  
     
     
         33 . The method of  claim 32  wherein said first metallization layer is nickel.  
     
     
         34 . The method of  claim 33  wherein said second metallization layer is copper.