Memory control apparatus and method for assigning a cache memory to store clean and dirty data based on a memory in the cache memories

Abstract

A memory control apparatus is interposed between a central processing unit and a memory device to store data includes a plurality of cache memories to temporarily store data which is transferred between the central processing unit and the memory device and a cache memory control unit having a selector for selecting a cache memory to store data which is transferred from the memory device. The memory control apparatus assigns cache memories to store clean data and dirty data, which is updated data corresponding to the clean data, in accordance with a data identifier, whether a slot number is odd or even, or a usable amount of memory in the cache memories. The memory control apparatus selects a cache memory to store the data so as to almost equalize usage in the plurality of cache memories, thereby controlling the allocation of the cache memories.

What is claimed is:  
     
         1 . A memory control apparatus, in a RAID structure which is interposed between a central processing unit and a memory device for storing data, having a cache memory for temporarily storing data of said memory device, and for transferring data between said central processing unit and said memory device, said memory control apparatus comprising: 
 a control unit for controlling said cache memory and for assigning a region of said cache memory for storing clean data, and another region of said cache memory for storing said dirty data which is updated data corresponding to the clean data,    wherein said control unit assigns the region of said cache memory in accordance with at least one of data identifier, a data slot number, or a usable memory amount in a cache memory when said control unit stores data in said cache memory.    
     
     
         2 . A memory control apparatus, which is interposed between a central processing unit and a memory device for storing data, having a cache memory for temporarily storing data of said memory device, for transferring data between said central processing unit and said memory device, said memory control apparatus comprising: 
 a control unit for controlling said cache memory and for assigning a region of said cache memory for storing clean data, and another region of said cache memory for storing said dirty data which is updated data corresponding to the clean data; and    means for storing cache using state information of each region of said cache memory,    wherein the region of said cache memory for storing is assigned in accordance with a comparison between said cache using state information of each region of said cache memory, when said control unit assigns a region of said cache memory for storing said clean data and a region of said cache memory for storing said dirty data.    
     
     
         3 . A memory control apparatus, which is interposed between a central processing unit and a memory device for storing data, having a plurality of cache memories for temporarily storing data of said memory device, and for transferring data between said central processing unit and said memory device, wherein each of said plurality of cache memories includes at least one region, said memory control apparatus comprising: 
 means for storing usable/unusable information for each region of each cache memory; and    a control unit for controlling said plurality of cache memories and for assigning a region of a cache memory for storing clean data, and another region of said cache memory for storing said dirty data, which is updated data concerned with said clean data, in accordance with said usable/unusable information,    wherein said control unit assigns a region of a cache memory to write-in, when write-in to the cache memory is to occur.    
     
     
         4 . In a memory control apparatus, which is interposed between a central processing unit and a memory device for storing data, having a cache memory for temporarily storing data of said memory device, for transferring data between said central processing unit and said memory device, a cache control method, responsive to a data write request from said central processing unit, comprising the steps of: 
 judging whether said write request is a write hit, and when said write request is a write hit, storing dirty data which is updated data concerned with clean data into a region of said cache memory and storing clean data into another region of said cache memory;    when said write request is not a write hit, reading cache using state information from means for storing cache using state information indicating using state for each region of said cache memory, and comparing said cache using state information of each of region of said cache memory; and    in response to said reading and comparing step, assigning a region of said cache memory for writing said clean data and a region of said cache memory for writing said dirty data.    
     
     
         5 . In a memory control apparatus, which is interposed between a central processing unit and a memory device for storing data, having a cache memory for temporarily storing data of said memory device, for transferring data between said central processing unit and said memory device, a cache control method, responsive to a data write request from said central processing unit, comprising the steps of: 
 determining whether said write request is a write hit, and when said write request is a write hit, storing dirty data which is updated data concerned with clean data into a region of said cache memory and storing into another region of said cache memory said clean data; and    when said write request is not a write hit, assigning a region of said cache memory for writing said clean data and another region of said cache memory for writing said dirty data in accordance with either one of a slot number to which an updating object number is stored or an identifier of data,    wherein said control unit assigns a region of said cache memory to write-in, when write-in to the cache memory is to occur.