Planarized semiconductor interconnect topography and method for polishing a metal layer to form wide interconnect structures

Abstract

The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by selectively etching a dielectric layer to form a plurality of posts surrounded by trenches. The trenches are filled with a conductive material, such as a metal, deposited to a level spaced above the upper surfaces of the dielectric layer and the posts. The surface of the conductive material is then polished to a level substantially coplanar with the upper surfaces of the dielectric layer and the posts. Advantageously, the polish rate of the conductive material above the trenches is substantially uniform. In this manner, the topological surface of the resulting interconnect level is substantially void of surface disparity.

What is claimed is:  
     
         1 . A method for forming a semiconductor topography having a substantially planar electrically conductive feature, comprising: 
 forming a plurality of trenches within a region of a dielectric layer to form from said dielectric layer a plurality of posts surrounded by said trenches;    filling said trenches with a conductive material; and    planarizing upper surfaces of said conductive material to an elevational level commensurate with upper surfaces of said dielectric layer.    
     
     
         2 . The method as recited in  claim 1  wherein forming said plurality of trenches comprises: 
 depositing a layer of photoresist upon said dielectric layer;  
 patterning said photoresist;  
 removing said photoresist from first regions of said dielectric layer where said trenches are to be formed while retaining said photoresist upon second regions of said dielectric layer from which said posts are to be formed; and  
 removing a portion of said dielectric layer from said first regions to form said trenches while retaining said dielectric layer in said second regions.  
 
     
     
         3 . The method as recited in  claim 1  wherein filling said trenches with a conductive material comprises depositing a metal.  
     
     
         4 . The method as recited in  claim 3  wherein said metal is selected from the group consisting of aluminum, copper, tungsten, molybdenum, tantalum, titanium, and alloys thereof.  
     
     
         5 . The method as recited in  claim 1  wherein said planarizing comprises chemical-mechanical polishing.  
     
     
         6 . The method as recited in  claim 1 , further comprising forming a passivation layer upon said conductive material and said dielectric layer.  
     
     
         7 . The method as recited in  claim 6 , further comprising removing portions of said passivation layer to form an opening above a portion of said conductive material.  
     
     
         8 . The method as recited in  claim 7 , further comprising removing said posts subsequent to said forming said passivation layer.  
     
     
         9 . The method as recited in  claim 1 , further comprising removing said posts subsequent to said filling.  
     
     
         10 . A substantially planar semiconductor topography comprising a conductive interconnect structure formed entirely within a trench and having at least one opening extending entirely through the conductive interconnect structure.  
     
     
         11 . The semiconductor topography as recited in  claim 10 , further comprising a dielectric material within said at least one opening.  
     
     
         12 . The semiconductor topography as recited in  claim 10 , further comprising a passivation layer upon said dielectric material.  
     
     
         13 . The semiconductor topography as recited in  claim 12  wherein said conductive interconnect structure comprises a bond pad and wherein said passivation layer has an opening formed therein above said conductive material.  
     
     
         14 . The semiconductor topography as recited in  claim 10  wherein said conductive interconnect structure comprises a bond pad.  
     
     
         15 . The semiconductor topography as recited in  claim 14  wherein said trench comprises a width of about 10 μm, said conductive material comprises a depth of at least about 0.2 μm, said opening comprises a width of about 10 μm, and said bond pad comprises a lateral dimension of between about 75 μm and about 100 μm.  
     
     
         16 . The semiconductor topography as recited in  claim 14  wherein said trench comprises a width of about 9 μm, said conductive material comprises a depth of at least about 0.2 μm, said opening comprises a width of about 1 μm, and said bond pad comprises a lateral dimension of between about 75 μm and about 100 μm.  
     
     
         17 . The semiconductor topography as recited in  claim 10  wherein said conductive interconnect structure comprises a conductive line.  
     
     
         18 . The semiconductor topography as recited in  claim 17  wherein said conductive line comprises a width of at least about 5 μm, said conductive material comprises a depth of at least about 0.2 μm, and said opening comprises a width of about 1 μm.  
     
     
         19 . The semiconductor topography as recited in  claim 10  wherein said conductive material comprises a metal.  
     
     
         20 . The semiconductor topography as recited in  claim 19  wherein said metal comprises a material selected form the group consisting of aluminum, copper, tungsten, molybdenum, tantalum, titanium, and alloys thereof.  
     
     
         21 . A substantially planar semiconductor topography comprising a conductive interconnect structure formed entirely within a trench and extending laterally between posts rising upward from a base of the trench.