Non-volatile semiconductor memory device

Abstract

A non-volatile semiconductor memory device usable in relatively wide applications and a method of manufacturing the same are provided. A NOR-type flash memory region ( 2 ) including a NOR-type memory cell transistor and a DINOR-type flash memory region ( 3 ) including a DINOR-type memory cell transistor are manufactured into a single semiconductor chip ( 1 ). A peripheral circuit region ( 7 ) including a transistor for a peripheral circuit or the like is manufactured into a region surrounding the NOR-type flash memory region ( 2 ) and the DINOR-type flash memory region ( 3 ). The peripheral circuit region ( 7 ) is shareable between the NOR-type flash memory region ( 2 ) and the DINOR-type flash memory region ( 3 ) by electrical connection to both of the regions.

What is claimed is:  
     
         1 . A method of manufacturing a non-volatile semiconductor memory device, comprising the steps of: 
 (a) preparing a semiconductor substrate;    (b) forming a plurality of gate structures on said semiconductor substrate, each of said plurality of gate structures including a multi-layer structure having a first insulation film, a floating gate electrode, a second insulation film and a control gate electrode stacked in the order named, said plurality of gate structures including first and second gate structures formed in first and second non-volatile memory cell regions, respectively;    (c) forming a first drain region in said first non-volatile memory cell region under a first drain formation condition by using said first gate structure as a mask;    (d) forming a second drain region in said second non-volatile memory cell region under a second drain formation condition by using said second gate structure as a mask;    (e) forming a first source region in said first non-volatile memory cell region under a first source formation condition by using said first gate structure as a mask, said first gate structure, said first drain region and said first source region constituting a first memory cell transistor having a first operating characteristic; and    (f) forming a second source region in said second non-volatile memory cell region under a second source formation condition by using said second gate structure as a mask, said second gate structure, said second drain region and said second source region constituting a second memory cell transistor having a second operating characteristic.    
     
     
         2 . The method according to  claim 1 , wherein: 
 said first memory cell transistor includes NOR-type memory cell transistor and said second memory cell transistor includes a DINOR-type memory cell transistor; and    said first and second drain formation conditions include conditions different from each other.    
     
     
         3 . The method according to  claim 2 , where: 
 said first and second drain formation conditions includes a partially common formation condition at least partially common to said first and second drain formation conditions.    
     
     
         4 . The method according to  claim 2 , wherein: 
 said first and second source formation conditions includes the same condition.