Dynamic memory word line driver scheme

Abstract

A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM is comprised of word lines, memory cells having enable inputs connected to the word lines, apparatus for receiving word line selecting signals at first logic levels V ss and V dd , and for providing a select signal at levels V ss and V dd , a high voltage supply source V pp which is higher in voltage than V dd , a circuit for translating the select signals at levels V ss and V dd to levels V ss and V pp and for applying it directly to the word lines for application to the enable inputs whereby an above V dd voltage level word line is achieved without the use of double boot-strap circuits.

What is claimed is:  
     
         1 . A random access memory comprising: 
 a controlled high voltage supply;    word lines;    memory cells, each comprising a charge storage capacitor and a pass transistor for storing a logic level on the storage capacitor, the pass transistor having an enable input connected to a word line;    word line selection circuits, each selection circuit comprising: 
 a pair of cross-coupled transistors coupled drain-to-gate at respective control nodes and having respective sources coupled to the controlled high voltage supply;  
 a first pull-down transistor coupled to one of the control nodes and gated by a word line select signal; and  
 a second pull-down transistor connected in parallel with the first pull-down transistor to said one of the control nodes, the gate of the second pull-down transistor being coupled to the other control node.