Flash memory device and fabricating method therefor

Abstract

A cell transistor of a flash memory device includes a semiconductor substrate, a source region, a drain region, a floating gate, an inter-gate insulating layer, and a control gate, wherein the floating gate has a tip protruding into an end portion of the source region. With the application of erasing voltages to the source region and the control gate, an intense electric field is induced on the tip of the floating gate. Accordingly, an erasing efficiency of the cell transistor can be enhanced.

What is claimed is:  
     
         1 . A cell transistor for a flash memory device, comprising: 
 a semiconductor substrate having a groove;    a source region disposed in the semiconductor substrate, wherein the groove is recessed into an end portion of the source region;    a drain region disposed in the semiconductor substrate to oppose the end portion of the source region;    a gate insulating layer disposed on the substrate; and    a floating gate, an inter-gate insulating layer, and a control gate sequentially disposed on the gate insulating layer, the floating gate overlapping with each opposing end portion of the source region and the drain region, wherein a portion of the floating gate protrudes to fill the groove in the source region.    
     
     
         2 . The cell transistor of  claim 1 , wherein the groove is a V-shaped groove, a U-shaped groove, or a rectangular groove.  
     
     
         3 . The cell transistor of  claim 1 , wherein the groove has a depth of about 0.1 μm to about 0.2 μm.  
     
     
         4 . The cell transistor of  claim 1 , wherein the groove has a width of about 0.1 μm to about 0.2 μm.  
     
     
         5 . The cell transistor of  claim 1 , wherein the floating gate overlaps with the source region at a width of about 0.4 μm to about 0.6 μm.  
     
     
         6 . A method of fabricating a cell transistor, comprising the steps of: 
 forming a groove recessed into a semiconductor substrate;    forming a source region in the semiconductor substrate, wherein the source region overlaps with the groove;    sequentially forming a gate insulating layer, a floating gate, an inter-gate layer, and a control gate on the semiconductor substrate, wherein the floating gate fills the groove of the semiconductor substrate; and    forming a drain region in the semiconductor substrate to thereby fabricate the cell transistor.    
     
     
         7 . The method of  claim 6 , wherein the step of forming the groove includes the steps of: 
 sequentially forming a buffer layer and an etching mask layer on the semiconductor substrate;    patterning the etching mask layer such that a portion of the buffer layer is exposed;    forming a spacer on the exposed portion of the buffer layer such that the exposed portion thereof is partially covered by the spacer;    forming the groove, recessed into the semiconductor substrate, by etching the buffer layer and the semiconductor substrate; and    removing the etching mask layer.    
     
     
         8 . The method of  claim 7 , further comprising the step of: 
 removing the buffer layer before the step of sequentially forming the gate insulating layer, the floating gate, the inter-gate layer, and the control gate.    
     
     
         9 . The method of  claim 7 , wherein the buffer layer and the etching mask layer are respectively made of first and second insulation materials, wherein the first and the second insulation material have different etching selectivities.  
     
     
         10 . The method of  claim 7 , wherein the buffer layer and the spacer are respectively made of first and second insulation materials, wherein the first and the second insulation material have different etching selectivities.  
     
     
         11 . The method of  claim 7 , wherein the buffer layer and the spacer are respectively made of first and second insulation materials, wherein the first and the second insulation material have an equal etching selectivity.  
     
     
         12 . The method of  claim 6 , wherein the source region is formed by ion implantation.  
     
     
         13 . The method of  claim 6 , wherein the groove is formed by a dry etching.  
     
     
         14 . The method of  claim 6 , wherein the groove is formed by a wet etching.  
     
     
         15 . A flash memory device fabricated by the method of  claim 6 , comprising: 
 the semiconductor substrate having the groove;    the source region disposed in the semiconductor substrate, wherein the groove is recessed into an end portion of the source region;    the drain region disposed in the semiconductor substrate to oppose an end portion of the source region;    the gate insulating layer disposed on the substrate; and    the floating gate, the inter-gate insulating layer, and the control gate sequentially disposed on the gate insulating layer, the floating gate overlapping with each opposing end portion of the source region and the drain region, wherein a portion of the floating gate protrudes to fill the groove in the source region.    
     
     
         16 . A method of fabricating a cell transistor for a flash memory of  claim 1 , comprising the steps of: 
 forming the groove recessed into the semiconductor substrate;    forming the source region in the semiconductor substrate, wherein the source region overlaps with the groove;    sequentially forming the gate insulating layer, the floating gate, the inter-gate layer, and the control gate on the semiconductor substrate, wherein the floating gate fills the groove of the semiconductor substrate; and    forming the drain region in the semiconductor substrate to thereby fabricate the cell transistor of  claim 1 .    
     
     
         17 . A transistor for a flash memory device, comprising: 
 a semiconductor substrate;    a source region and a drain region opposing each other in the semiconductor substrate;    a floating gate disposed over the source and the drain region to overlap with opposing end portions thereof, wherein the floating gate has a tip protruding into the end portions of the source region;    a gate insulating layer interposed between the semiconductor substrate and the floating gate; and    an inter-gate insulating layer and a control gate sequentially disposed on the floating gate.