US2004089917A1PendingUtilityA1

Three-dimensional memory array and method of fabrication

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Priority: Apr 28, 2000Filed: Oct 20, 2003Published: May 13, 2004
Est. expiryApr 28, 2020(expired)· nominal 20-yr term from priority
Inventors:N. Johan KnallMark G. Johnson
H10D 88/01H10D 88/00H10D 84/038H10B 20/20G11C 16/0466
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Claims

Abstract

A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A three dimensional multi-level memory array disposed above a substrate, the array comprising a plurality of memory cells, each memory cell comprising a silicon nitride antifuse.  
     
     
         2 . The array of  claim 1 , further comprising p+n− diodes or p−n+ diodes.

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