US2004089938A1PendingUtilityA1

Bonding pad design

Assignee: LSI LOGIC CORPPriority: Nov 1, 2001Filed: Oct 27, 2003Published: May 13, 2004
Est. expiryNov 1, 2021(expired)· nominal 20-yr term from priority
H10W 72/29H10W 72/9232H10W 72/251H10W 72/012Y10T29/49155
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Claims

Abstract

A bonding pad for an integrated circuit, having a conductive base layer. The conductive base layer has slots formed in it, where the slots extend completely through the conductive base layer. An insulating layer is disposed on top of the conductive base layer. The insulating layer protrudes into the slots of the conductive base layer. The insulating layer also includes a low k material. A conductive top layer is disposed on top of the insulating layer.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A bonding pad for an integrated circuit, the bonding pad comprising: 
 a conductive base layer having slots formed therein, the slots extending completely through the conductive base layer,    an insulating layer disposed on top of the conductive base layer, the insulating layer protruding into the slots of the conductive base layer, and the insulating layer including a low k material, and    a conductive top layer disposed on top of the insulating layer.    
     
     
         2 . The bonding pad of  claim 1  further comprising a plurality of vias extending through the insulating layer and electrically connecting the conductive base layer to the conductive top layer at peripheral portions of the conductive base layer and the conductive top layer.  
     
     
         3 . The bonding pad of  claim 1  wherein the insulating layer comprises a base oxide layer on top of the conductive base layer, a low k dielectric layer on top of the base oxide layer, and a cap oxide layer between the low k dielectric layer and the conductive top layer.  
     
     
         4 . The bonding pad of  claim 1  wherein both the conductive base layer and the conductive top layer comprise a metal selected from the group consisting of aluminum, copper, nickel, ruthenium, titanium, tungsten, platinum, and gold.  
     
     
         5 . The bonding pad of  claim 1  wherein the slots of the conductive base layer comprise a pattern of substantially parallel slots.  
     
     
         6 . The bonding pad of  claim 1  wherein the slots of the conductive base layer have a width of about eleven microns and a spacing of about three microns.  
     
     
         7 . The bonding pad of  claim 1  wherein the insulating layer has a thickness measured between the conductive base layer and the conductive top layer of from about three thousand angstroms to about fifteen thousand angstroms.  
     
     
         8 . The bonding pad of  claim 1  further comprising multiple layers of the conductive base layer and the overlying insulating layer below the conductive top layer.  
     
     
         9 . An integrated circuit, the improvement comprising the bonding pad of  claim 1 .  
     
     
         10 . A method for forming a bonding pad on a substrate, the method comprising the steps of: 
 forming a conductive base layer on the substrate, the conductive base layer having slots extending completely through the conductive base layer,    forming an insulating layer on top of the conductive base layer, the insulating layer protruding into the slots of the conductive base layer, and the insulating layer including a low k material, and    forming a conductive top layer on top of the insulating layer.    
     
     
         11 . The method of  claim 10  further comprising the step of forming a plurality of conductive vias extending through the insulating layer and electrically connecting the conductive base layer to the conductive top layer at peripheral portions and adjacent the slots of the conductive base layer and the conductive top layer.  
     
     
         12 . The method of  claim 10  wherein the step of forming the insulating layer comprises the steps of: 
 forming a base oxide layer on top of the conductive base layer, forming a low k dielectric layer on top of the base oxide layer, and forming a cap oxide layer between the low k dielectric layer and the conductive top layer.  
 
     
     
         13 . The method of  claim 10  wherein both the conductive base layer and the conductive top layer comprise a metal selected from the group consisting of aluminum, copper, nickel, ruthenium, titanium, tungsten, platinum, and gold.  
     
     
         14 . The method of  claim 10  wherein the slots of the conductive base layer comprise a pattern of substantially parallel slots.  
     
     
         15 . The method of  claim 10  wherein the slots of the conductive base layer have a width of about eleven microns and a spacing of about three microns.  
     
     
         16 . The method of  claim 10  wherein the insulating layer has a thickness measured between the conductive base layer and the conductive top layer of from about three thousand angstroms to about fifteen thousand angstroms.  
     
     
         17 . The method of  claim 10  further comprising forming multiple layers of the conductive base layer and the overlying insulating layer below the conductive top layer.  
     
     
         18 . An integrated circuit, the improvement comprising a bonding pad formed according to the method of  claim 10 .  
     
     
         19 . An integrated circuit, the improvement comprising a bonding pad having: 
 a conductive base layer having slots formed therein, the slots extending completely through the conductive base layer,    an insulating layer disposed on top of the conductive base layer, the insulating layer protruding into the slots of the conductive base layer, and the insulating layer including a low k material, and    a conductive top layer disposed on top of the insulating layer.    
     
     
         20 . The integrated circuit of  claim 19  wherein the insulating layer comprises a base oxide layer on top of the conductive base layer, a low k dielectric layer on top of the base oxide layer, and a cap oxide layer between the low k dielectric layer and the conductive top layer.  
     
     
         21 . The integrated circuit of  claim 19  wherein the slots of the conductive base layer have a width of about eleven microns and a spacing of about three microns.  
     
     
         22 . The integrated circuit of  claim 19  wherein the insulating layer has a thickness measured between the conductive base layer and the conductive top layer of from about three thousand angstroms to about fifteen thousand angstroms.  
     
     
         23 . The integrated circuit of  claim 19  further comprising multiple layers of the conductive base layer and the overlying insulating layer below the conductive top layer.

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