Memory control apparatus and method for digital signal processing

Abstract

A memory control apparatus and method for digital signal processing capable of operating with a plurality of digital signal processors (DSPs) using a single memory slot and a buffer. The apparatus includes at least one DSP for processing different signals, a flash memory which can record and reproduce a digital signal, a plurality of selection switches, located on signal lines between the DSP and the flash memory, for switching input/output of signals, a three-state buffer which selectively outputs insert information of the flash memory to the DSPs according to a control signal, a control unit for providing the control signal for controlling switching of the signals, and a key input unit for determining input/output operation modes. The control unit records or reproduces the data in the flash memory according to the operation mode determined through the key input unit. The memory and the buffer are commonly used when a plurality of DSPs are operated, and thus an operation system having a simple construction is provided.

What is claimed is:  
     
         1 . A memory control apparatus, adapted to operate with a plurality of digital signal processors (DSPs), the memory control apparatus comprising: 
 a switch, adapted to selectively route signals for input to the DSPs from a memory and for output from the DSPs to the memory;    a buffer, adapted to selectively output to the DSPs memory information indicating that the memory is available; and    a controller, adapted to control the switch to route the signals to and from the memory and DSPs and to control the buffer to selectively output the memory information.    
     
     
         2 . A memory control apparatus as claimed in  claim 1 , wherein: 
 the memory is a removable memory, and the memory information indicates that the memory has been inserted into a port for access by the memory control apparatus.    
     
     
         3 . A memory control apparatus as claimed in  claim 2 , wherein: 
 the memory is a flash memory.    
     
     
         4 . A memory control apparatus as claimed in  claim 1 , wherein: 
 the switch includes a plurality of selection switches, coupled between the DSPs and the memory, which are controlled by the controller.    
     
     
         5 . A memory control apparatus as claimed in  claim 1 , wherein: 
 the buffer includes a three-state buffer which selectively outputs the memory information of the memory to the DSPs as controlled by the controller.    
     
     
         6 . A memory control apparatus as claimed in  claim 1 , further comprising: 
 a key input unit, adapted to indicate an operation mode; and    wherein the control unit controls recording of data in the memory or reproduction of data from the memory according to the operation mode indicated by the key input unit.    
     
     
         7 . A memory control apparatus as claimed in  claim 1 , wherein: 
 one of the DSPs is employed with a digital still camera and another of the DSPs is employed with a digital video camera; and    wherein the controller controls the switch to route the signals to and from the memory and the DSPs of the digital still camera and digital video camera.    
     
     
         8 . A method for controlling a memory control apparatus to operate with a plurality of digital signal processors (DSPs), the method comprising: 
 controlling a switch to selectively route signals for input to the DSPs from a memory and for output from the DSPs to the memory; and    controlling a buffer to selectively output to the DSPs memory information indicating that the memory is available.    
     
     
         9 . A method as claimed in  claim 8 , wherein: 
 the memory is a removable memory, and the memory information indicates that the memory has been inserted into a port for access by the memory control apparatus.    
     
     
         10 . A method as claimed in  claim 9 , wherein: 
 the memory is a flash memory.    
     
     
         11 . A method as claimed in  claim 8 , wherein: 
 the switch includes a plurality of selection switches, coupled between the DSPs and the memory; and    the switch controlling step includes controlling the plurality of switches.    
     
     
         12 . A method as claimed in  claim 8 , wherein: 
 the buffer includes a three-state buffer; and    the buffer controlling step controls the three-state buffer to selectively output the memory information of the memory to the DSPs.    
     
     
         13 . A method as claimed in  claim 8 , further comprising: 
 receiving information from a key input unit indicating an operation mode; and    controlling recording of data in the memory or reproduction of data from the memory according to the operation mode indicated by the key input unit.    
     
     
         14 . A method as claimed in  claim 8 , wherein: 
 one of the DSPs is employed with a digital still camera and another of the DSPs is employed with a digital video camera; and    wherein the switch controlling step controls the switch to route the signals to and from the memory and the DSPs of the digital still camera and digital video camera.    
     
     
         15 . A computer-readable medium of instructions for controlling a memory control apparatus to operate with a plurality of digital signal processors (DSPs), the computer-readable medium of instructions comprising: 
 a first set of instructions, adapted to control a switch to selectively route signals for input to the DSPs from a memory and for output from the DSPs to the memory; and    a second set of instructions, adapted to control a buffer to selectively output to the DSPs memory information indicating that the memory is available.    
     
     
         16 . A computer-readable medium of instructions as claimed in  claim 15 , wherein: 
 the memory is a removable memory, and the memory information indicates that the memory has been inserted into a port for access by the memory control apparatus.    
     
     
         17 . A computer-readable medium of instructions as claimed in  claim 16 , wherein: 
 the memory is a flash memory.    
     
     
         18 . A computer-readable medium of instructions as claimed in  claim 15 , wherein: 
 the switch includes a plurality of selection switches, coupled between the DSPs and the memory; and    the first set of instructions is adapted to control the plurality of switches.    
     
     
         19 . A computer-readable medium of instructions as claimed in  claim 15 , wherein: 
 the buffer includes a three-state buffer; and    the second set of instructions is adapted to control the three-state buffer to selectively output the memory information of the memory to the DSPs.    
     
     
         20 . A computer-readable medium of instructions as claimed in  claim 15 , further comprising: 
 a third set of instructions, adapted to control the memory control apparatus to receive information from a key input unit indicating an operation mode; and    a fourth set of instructions, adapted to control the memory control apparatus to control recording of data in the memory or reproduction of data from the memory according to the operation mode indicated by the key input unit.    
     
     
         21 . A computer-readable medium of instructions as claimed in  claim 15 , wherein: 
 one of the DSPs is employed with a digital still camera and another of the DSPs is employed with a digital video camera; and    wherein the first set of instructions controls the switch to route the signals to and from the memory and the DSPs of the digital still camera and digital video camera.