Memory controller, interface device and method using a mode selection signal to support different types of memories

Abstract

A memory controller, interface (I/F) device and method for controlling data communication with a memory device are disclosed. The memory controller allows different types of memory devices to be supported. The memory controller has a first buffer for capturing data at a rising edge of a timing control signal and a second buffer for capturing data at a falling edge of the timing control signal. A mode controller controls or adjusts the timing control signal depending on which one of single data rate (SDR) synchronous dynamic random access memory (SDRAM) mode and double date rate (DDR) mode is selected in response to a mode selection or switch signal. In SDR SDRAM mode, a clock signal is supplied to only the first buffer. In DDR mode, a data strobe signal is supplied to both the first and second buffers. The memory controller may also include a level adjuster for adjusting voltage levels of signals transferred between the memory device and buffers.

1 . A memory controller for controlling data communication of a plurality of memory device types, comprising: 
 a timing adjuster for adjusting buffer timing of data transfer between a memory device and a data bus by controlling a timing control signal,    said timing adjuster including    a mode controller for controlling the timing control signal to meet timing requirements of each of a plurality of memory device types of a different data rate type depending on a mode selection signal inputted from outside, wherein,    the mode selection signal is based on the data rate type of the memory device type connected to the memory controller.    
     
     
         2 . The memory controller according to  claim 1 , further comprising: 
 a level adjuster for adjusting a voltage level of data to be transferred between the memory device and the data bus depending on the type of the memory device.    
     
     
         3 . An interface device connecting a processor and a memory device, comprising: 
 a memory controller for controlling data communication with the memory device,    wherein the memory controller comprises    a timing adjuster for adjusting timing of data transfer between the memory device and a data bus by controlling a buffer timing control signal,    said timing adjuster including a mode controller for controlling the timing control signal to meet timing requirements of a selected one of a plurality memory device types of different data rate type, depending on a mode selection signal inputted from outside.    
     
     
         4 . The interface device according to  claim 3 , wherein the interface device and the processor are formed on a single semiconductor chip as an integrated circuit.