Semiconductor device and method and apparatus for testing such a device

Abstract

A semiconductor device can be subjected to scan testing by using an input scan test vector. This input scan test vector is processed by the device to produce an output scan test vector, which can be used for diagnostic purposes with respect to the device. There are certain locations in this output scan test vector that may be indeterminate in value, even for a correctly functioning device. In other words, it is not possible to predict beforehand what values the output scan test vector will have at these locations. Therefore, an output mask vector is provided that identifies those locations in the output scan test vector that are indeterminate. This mask vector is then combined with the output scan test vector using a logical operation to produce a determinate masked output scan test vector. For example, if all the indeterminate locations are flagged by a 1 in the mask vector, then using OR for the logical operation will ensure that the output for these locations is always a 1. Having a fully determinate output vector allows a signature to be calculated for this vector, and this signature will have a predetermined value for a correctly functioning device.

1 . A method for scan testing a semiconductor device comprising the steps of: 
 providing an input scan test vector;    processing the input scan test vector through the device to produce an output scan test vector comprising a sequence of locations each having a value, wherein one or more locations in said sequence are, a priori, indeterminate in value, even if said device is functioning correctly;    providing an output mask vector, wherein said mask vector identifies those one or more locations in the output scan test vector that are, a priori, indeterminate in value; and    combining the output scan test vector with said output mask vector using a logical operation to produce a determinate masked output scan test vector.    
     
     
         2 . The method of  claim 1 , further comprising the step of producing a signature from at least a portion of the masked output scan test vector.  
     
     
         3 . The method of  claim 2 , wherein the signature is produced using a hashing function.  
     
     
         4 . The method of  claim 2 , wherein the signature is produced using a linear feedback shift register.  
     
     
         5 . The method of  claim 2 , further comprising the step of comparing said signature with a predetermined value to determine whether or not the device is functioning correctly.  
     
     
         6 . The method of  claim 5 , wherein said step of comparing is performed within said semiconductor device.  
     
     
         7 . The method of  claim 6 , further comprising the step of sending an interrupt if the signature does not match said predetermined value.  
     
     
         8 . The method of  claim 1 , wherein the output mask vector is provided in compressed form, and the method further comprises the step of decompressing the output mask vector prior to combining with the output scan test vector.  
     
     
         9 . The method of  claim 8 , wherein the output mask vector is compressed using run length encoding.  
     
     
         10 . The method of  claim 1 , wherein the output mask vector comprises a sequence of locations, each having a binary value and corresponding to a different one of the locations in the output scan test vector, and wherein a location in the output mask vector has a binary value of 1 if the corresponding location in the output scan test vector is, a priori, indeterminate, and a binary value of 0 otherwise.  
     
     
         11 . The method of  claim 10 , wherein said logical operation comprises an OR function.  
     
     
         12 . The method of  claim 1 , wherein the output mask vector comprises a sequence of locations, each having a binary value and corresponding to a different one of the locations in the output scan test vector, and wherein a location in the output mask vector has a binary value of 0 if the corresponding location in the output scan test vector is, a priori, indeterminate, and a binary value of 1 otherwise.  
     
     
         13 . The method of  claim 12 , wherein said logical operation comprises an AND function.  
     
     
         14 . The method of  claim 1 , wherein the masked output scan test vector comprises a sequence of locations, each corresponding to a different one of the locations in the output scan test vector, and wherein all those locations in the masked output scan test vector that correspond to a location in the output scan test vector that is, a priori, indeterminate have the same value in the masked output scan test vector.  
     
     
         15 . The method of  claim 1 , further comprising the step of comparing the masked output scan test vector against a predetermined vector in order to ascertain whether or not the device is functioning correctly.  
     
     
         16 . The method of  claim 1 , wherein the masked output scan test vector is produced from the output scan test vector by excising those locations in the output scan test vector that are, a priori, indeterminate in value.  
     
     
         17 . A method for scan testing a device, comprising the steps of: 
 processing an input scan test vector through the device to produce an output scan test vector;    combining the output scan test vector with an output mask vector in order to produce a determinate masked output scan test vector.    
     
     
         18 . Apparatus for scan testing a device comprising: 
 means for providing an input scan test vector, wherein the input scan test vector is to be processed through the device in order to produce an output scan test vector comprising a sequence of locations each having a value, wherein one or more locations in said sequence are, a priori, indeterminate in value, even if said device is functioning correctly; and    means for providing an output mask vector, wherein said mask vector identifies those locations in the output scan test vector that are indeterminate.    
     
     
         19 . Test control apparatus comprising: 
 a communications interface that is operable for connection to a test device undergoing a scan test;    a stored input scan vector for supply to the test device via said communications interface; and    a stored mask vector for supply to the test device via said communications interface.    
     
     
         20 . The test control apparatus of  claim 19 , wherein a signature representing the outcome of a scan test is receivable back from the test device via said communications interface.  
     
     
         21 . The test control apparatus of  claim 19 , wherein an interrupt signal is receivable back from the test device via said communications interface if a signature representing the outcome of a scan test does not match a predetermined value.  
     
     
         22 . The test control apparatus of  claim 21 , wherein said predetermined value is supplied to the test device via said communications interface.  
     
     
         23 . A semiconductor device including support for scan testing, said device including: 
 at least one port for receiving an input scan test vector and a mask vector;    a scan sequence, wherein the result of passing the input scan test vector through the scan sequence is an output scan test vector; and    logic for combining the mask vector and the output scan test vector to generate a masked output scan test vector.    
     
     
         24 . The device of  claim 23 , wherein the output scan test vector comprises a sequence of locations each having a value, wherein one or more locations in said sequence are, a priori, indeterminate in value, even if said device is functioning correctly, and wherein the mask vector identifies the one or more locations in the output scan test vector that are, a priori, indeterminate in value.  
     
     
         25 . The device of  claim 24 , further comprising a signature generator for operating upon the masked output scan test vector.  
     
     
         26 . The device of  claim 25 , wherein the signature generator determines a hashing function of the masked output scan test vector.  
     
     
         27 . The device of  claim 25 , wherein the signature generator comprises a linear feedback shift register.  
     
     
         28 . The device of  claim 25 , further comprising a comparator for confirming that a signature produced by the signature generator matches an expected value for the signature.  
     
     
         29 . The device of  claim 28 , wherein the device signals an interrupt, if the comparator does not detect a match.  
     
     
         30 . The device of  claim 23 , further comprising a decompression unit attached to said at least one port, wherein the mask vector is received by the device in compressed format.  
     
     
         31 . The device of  claim 24 , wherein the output mask vector comprises a sequence of locations, each having a binary value and corresponding to a different one of the locations in the output scan test vector, and wherein a location in the output mask vector has a binary value of 1 if the corresponding location in the output scan test vector is, a priori, indeterminate, and a binary value of 0 otherwise.  
     
     
         32 . The device of  claim 31 , wherein said logic comprises an OR gate.  
     
     
         33 . The device of  claim 24 , wherein the output mask vector comprises a sequence of locations, each having a binary value and corresponding to a different one of the locations in the output scan test vector, and wherein a location in the output mask vector has a binary value of 0 if the corresponding location in the output scan test vector is, a priori, indeterminate, and a binary value of 1 otherwise.  
     
     
         34 . The device of  claim 33 , wherein said logic comprises an AND gate.  
     
     
         35 . The device of  claim 24 , wherein said logic generates the masked output scan test vector from the output scan test vector and the output mask vector by excising those locations in the output scan test vector that are, a priori, indeterminate in value.  
     
     
         36 . Apparatus supporting a scan test facility, said apparatus comprising: 
 means for receiving an input scan test vector;    means for processing the input scan test vector to produce an output scan test vector comprising a sequence of locations each having a value, wherein one or more locations in said sequence are, a priori, indeterminate in value, even if the device is functioning correctly;    means for receiving an output mask vector, said mask vector identifying the one or more locations in the output scan test vector that are, a priori, indeterminate in value; and    means for combining the output scan test vector with said output mask vector using a logical operation in order to produce a determinate masked output scan test vector.    
     
     
         37 . Apparatus comprising: 
 a control facility;    a component to undergo a scan test; and    a communications link between the control facility and said component;    wherein said component includes:    a scan sequence for generating an output scan vector from an input scan vector as a result of a scan test; and    logic for combining the output scan vector with a mask vector to generate a masked output scan test vector.    
     
     
         38 . The apparatus of  claim 37 , wherein a scan test is performed in the component in response to a command from the control facility.  
     
     
         39 . The apparatus of  claim 37 , wherein the component further includes a signature generator for calculating a signature from the masked output scan test vector.  
     
     
         40 . The apparatus of  claim 39 , wherein the component sends an interrupt to the control facility, if the calculated signature does not match an expected value.