Predictive snooping of cache memory for master-initiated accesses

Abstract

When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.

1 . A method for reading data in a burst from a memory to a PCI master in response to a burst read access by said PCI master, said burst read access identifying a starting address in a line Ln of said memory, in a system which includes a CPU having a first level cache, comprising the steps of: 
 reading data from said memory according to said burst read access; and    simultaneously performing an inquiry cycle of line Ln+1 in said first level cache.