Burrless castellation via process and product for plastic chip carrier

Abstract

This invention incorporates a new process and structure for manufacturing castellation via in plastic chip carrier. It allows the creation of uniform side wall contacts in the shape of half-cylinders, devoid of any burrs and power dust particles, which when present in a plastic chip carrier, would prevent reliable electrical contacts by causing either short or open circuits. Thus the invention enables plastic chip carrier as a practical way of replacing traditional ceramic chip carriers.

What is claimed is:  
     
         1 . In a process for manufacturing a leadless semiconductor chip carrier which includes conductive metal plating the carrier substrate having a plurality of routable holes to form a conductive metal plated chip carrier substrate, and, routing one or more slots in said conductive metal plated chip carrier substrate, the improvement for preventing burrs comprising said conductive metal plating is performed (a) prior to making said routing one or more slots by a thin conductive metal plating with a thickness in the range of about 2 microns to about 6 microns and (b) subsequent to routing of said slots, thickening said conductive metal plating to a final thickness.  
     
     
         2 . The process defined in  claim 1  wherein said conductive metal is copper and said final thickness is in that range of between about 15 microns to about 25 microns.  
     
     
         3 . In a process for further preventing burrs in the process prescribed in  claim 1 , whereby a coating layer such as UV curable ink is applied after the thin conductive metal plating and pattern etching, used as a protection for the thin conductive metal plating during routing, and stripped off after routing whereby said coating layer provides backing support and prevents the thin copper from being pulled off.  
     
     
         4 . The process defined in  claim 3  wherein said conductive metal is copper and said final thickness is in that range of between about 15 microns to about 25 microns.  
     
     
         5 . In a leadless semiconductor chip carrier having a conductive metal plating on a substrate and one or more machined routings formed through said conductive metal plating and substrate, the improvement wherein said conductive metal plating is comprised of a first thin conductive metal layer applied prior to said one or more machined routings and at least a second thicker conductive metal layer applied after said machined routing to a final thickness of said conductive metal plating.  
     
     
         6 . The chip carrier defined in  claim 5  wherein said first thin layer has a thickness in the range of about 2 microns to about 6 microns.  
     
     
         7 . The chip carrier defined in  claim 6  wherein said final thickness is in the range of about 15 microns to about 25 microns.  
     
     
         8 . The chip carrier defined in  claim 5  wherein said conductive metal is copper.  
     
     
         9 . The chip carrier defined in  claim 6  wherein said conductive metal is copper.  
     
     
         10 . The chip carrier defined in  claim 7  wherein said conductive metal is copper.