Chip transporter
Abstract
Apparatus for transporting semiconductor chips defining electronic circuitry or the like including a base layer of deformable anti-static film; a thin plastic body layer having a first surface to which the base layer adheres, the body layer having one or more cavities shaped to hold chips; and an anti-static holding layer adhering to a surface of the body layer opposite the base layer, the holding layer being less deformable than the base layer and provided with openings through which a chip defining electronic circuitry or the like may be inserted into one of the cavities and will be held in place therein by the holding layer.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A protective carrier for electronic circuitry on a semiconductor chip comprising a base layer of deformable anti-static film; a thin plastic body layer halving a first surface to which the base layer adheres, the body layer having a cavity shaped to hold a semiconductor chip; and an anti-static holding layer adhering to a surface of the body layer opposite the base layer, the holding layer being less deformable than the base layer and provided with an opening through which a chip may be inserted into the cavity to be held in place therein by the holding layer.
2 . A protective carrier for electronic circuitry on a generally-flat semiconductor chip comprising a stiff layer of material defining a volume into which the chip may be placed, a generally-flat distendable surface of anti-static material larger than a largest flat surface of the chip adhering to the stiff layer of material and closing the volume on one side, and a generally-flat layer of anti-static material larger than a largest flat surface of the chip adhering to the stiff layer of material at a side opposite the one side, the last-mentioned generally-flat layer of anti-static material having an opening through which the chip may be inserted into the volume and removed.
3 . A protective carrier for electronic circuitry on a generally-flat semiconductor chip comprising a stiff layer of material defining a volume into which the chip may be placed, a generally-flat surface of anti-static material larger than a largest flat surface of the chip adhering to the stiff layer of material and closing the volume on one side, a generally-flat layer of anti-static material larger than a largest flat surface of the chip adhering to the stiff layer of material to effectively close the volume at a side opposite the one side, and means providing an opening through which the chip may be inserted into the volume and removed.Join the waitlist — get patent alerts
Track US2004144687A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.