Method for making a nano-stamp and for forming, with the stamp, nano-size elements on a substrate

Abstract

The stamping process and a method of fabrication of nano-stamps with characteristic dimensions below 1 nm and up to 0.1 micron intended for usage in making patterns of characteristic dimensions same as those of the nano-stamp on surface of a substrate is provided. In the process a very hard stamp is fabricated by first depositing alternating layers of two materials, one of which has very high hardness, on some sacrificial substrate via PVD, CVD or any other deposition procedure that produces alternating layers of selected thickness, from sub 1 nm to above 100 nm. The layered film is then polished to atomically smooth finish perpendicular to the plane of the layers and etched to produce dips in the softer layers These steps produce a grid of parallel elevations and valleys on the etched surface, which now can be used as a mold to stamp out patterns on a substrate of lower hardness than the hardness of the elevated layers. If the substrate is stamped twice with turning of the stamp 90 degrees between first and second stampings, a square pattern of hills and valleys is formed, which can be used for magnetic memory storage by subsequently sputtering magnetic material on the tops of the elevations or hills.

I claim:  
     
         1 . A method for making a nano-stamp comprising the steps of: 
 sputtering a first [thin] layer of one type of material on a substrate;    sputtering a second [thin] layer of a second material on top of the first layer;    repeating the two previous steps until a superlattice structure having a desired number of alternate layers of different material has been formed;    cutting through the superlattice structure transverse to the layers;    atomically polishing the cut surface of the superlattice; and    applying an etchant material to etch away the softer one of the alternate layers of material in the superlattice to a sufficient depth thereby to form a nano-stamp comprising a grid of very thin edge lines separated by very thin spacings on the order of 25 nanometers or less and as low as 1 nanometer.    
     
     
         2 . The method of  claim 1  wherein the layer of harder material is made of ZrB 2 .  
     
     
         3 . The method of  claim 1  wherein the layer of softer material is made of W.  
     
     
         4 . The method of  claim 1  wherein the etchant includes sulfuric acid.  
     
     
         5 . A nano-stamp comprising a block having a grid surface comprising a plurality of very thin line edges of relatively hard material separated by alternate very thin layers of a softer material with valleys being formed in the softer material at a polished surface of the block and between the edge lines of harder material by an etchant thereby to form a plurality of side-by-side rigid line edges separated by valleys whereby the center-to-center dimension between adjacent grid line edges is between 1 and 25 nanometers.  
     
     
         6 . The nano-stamp of  claim 5  wherein the thin edge lines are made of ZrB 2 .  
     
     
         7 . The nano-stamp of  claim 5  wherein the thin alternate layers are made of W.  
     
     
         8 . The method of forming a high density nano-electronic device comprising: a lattice of elements or elevations having very small dimensions between approximately 1 and approximately 25 nanometers in lateral extent comprising the steps of: 
 providing a first substrate of one material;    providing a thinner layer of a second substrate of a second material on top of the first substrate;    stamping the second layer of substrate material with a nano-stamp comprising a block having a grid surface comprising a plurality of very closely spaced line edges of relatively hard material separated by alternate very thin layers of a softer material with valleys being formed in the softer material between the line edges of the harder material by an etchant thereby to form a plurality of side-by-side rigid line edges separated by valleys on a polished surface of the block whereby the center-to-center dimension between grid line edges is between approximately 2 and approximately 25 nanometers;    rotating the nanostamp so that the line edges of the nano-stamp will traverse or cross the lines formed in the upper substrate by the first stamping;    stamping the upper substrate a second time with the nano-stamp;    removing the nano-stamp to leave elevations, tops or cells with valleys therebetween where the bottom of each valley is substantially the first substrate material and the elevations, tops or cells being formed substantially of the upper substrate material; and,    sputtering a conductive material on the elevations, tops or cells formed in the upper substrate layer, thereby to form a high density micro-electronic device.    
     
     
         9 . The method of  claim 8  wherein said conductive material is magnetic nickel.  
     
     
         10 . The method of  claim 8  wherein said first substrate material is Si.  
     
     
         11 . The method of  claim 8  wherein said second substrate material is SiO 2 .  
     
     
         12 . The method of  claim 8  wherein said first substrate material is made of a conductive material.  
     
     
         13 . The method of  claim 8  wherein said second substrate material is made of a piezoelectric material.  
     
     
         14 . A high density nano-electronic device comprising: 
 a lattice of elements, elevations tops or cells having very small dimensions between approximately 1 and approximately 25 nanometers on lateral extent in a second substrate material disposed on top of a first substrate material; each element, elevation, top or cell having a generally square configuration and a lateral extent of between 1 and 25 nanometer; and, a conductive material in a small layer on each element, elevation, top or cell formed in the upper substrate layer.    
     
     
         15 . The nano-electronic device of  claim 14  wherein said conductive material is magnetic nickel.  
     
     
         16 . The nano-electronic device of  claim 14  wherein said first substrate is Si.  
     
     
         17 . The nano-electronic device of  claim 14  wherein said second substrate material is SiO 2 .  
     
     
         18 . The nano-electronic device of  claim 14  wherein said first substrate is made of a conductive material.  
     
     
         19 . The nano-electronic device of  claim 14  wherein said second substrate material is made of a piexoelectric material.  
     
     
         20 . A process of nano-stamping and a method for fabricating a nano-stamp for said process to use for forming nano-size patterns on a substrate, comprising the steps of: fabricating a nano-stamp from two materials, at least one of which is significantly harder than the other material, by utilizing PVD, CVD, or any other method for forming nano-layered two-dimensional superlattices; cleaving or cutting the nano-layered film to obtain a section perpendicular to the plain of the layers; polishing and etching this surface to obtain uniform elevated lines of the harder material and grooves of the softer material forming a nano-stamp; selecting an appropriate substrate; pressing or indenting the nanostamp into the surface of the substrate whereby a set of grooves is formed on the surface of the substrate mirroring those on the surface of the nano-stamp; lifting the nano-stamp from the surface, turning it 90 degrees about the stamping axis and repeating the pressing or indenting procedure thus producing a square pattern of elevations and valleys; removing the nanostamp from the surface of the substrate; and, sputtering metallic material on the top of the elevations to produce magnetic memory-type device.