Gate edge diode leakage reduction

Abstract

An embodiment of the invention is an integrated circuit 2 having halo atoms 12 concentrated at a gate side of a channel region and impurity atoms 14 within the channel region. Another embodiment of the invention is a method of manufacturing an integrated circuit that includes the implantation of impurity atoms 14 into a semiconductor substrate 11.

1 . An integrated circuit comprising: 
 a semiconductor substrate;    a gate coupled to said semiconductor substrate;    a source region within said semiconductor substrate, said source region electrically coupled to said gate;    a drain region within said semiconductor substrate, said drain region electrically coupled to said gate;    a source extension region within said semiconductor substrate, said source extension region coupled to said source region;    a drain extension region within said semiconductor substrate, said drain extension region coupled to said drain region;    a channel region within said semiconductor substrate, said channel region coupled to said gate, said source extension region, and said drain extension region;    halo atoms within said channel region, said halo atoms being more concentrated at a gate side of said channel region, and said halo atoms being less concentrated at a source extension region side and a drain extension region side of said channel region; and    impurity atoms within said integrated circuit.    
     
     
         2 . The integrated circuit of  claim 1  wherein said gate, said source region, and said drain region form a CMOS transistor.  
     
     
         3 . The integrated circuit of  claim 1  wherein said impurity atoms are fluorine.  
     
     
         4 . The integrated circuit of  claim 1  wherein said halo atoms are boron.  
     
     
         5 . A method of manufacturing a semiconductor wafer comprising: 
 forming a gate over a semiconductor substrate;    implanting a source extension region and a drain extension region into said semiconductor substrate;    implanting a halo region into said semiconductor substrate;    implanting impurity atoms into said semiconductor substrate;    implanting a source and a drain into said semiconductor substrate; and    heating said semiconductor wafer to diffuse atoms in said halo region.    
     
     
         6 . The method of  claim 5  wherein said source extension region and said drain extension region comprise arsenic atoms.  
     
     
         7 . The method of  claim 5  wherein said halo region comprises boron atoms.  
     
     
         8 . The method of  claim 5  wherein impurity atoms are fluorine atoms.  
     
     
         9 . A method of manufacturing a semiconductor wafer comprising: 
 forming a gate over a semiconductor substrate, said gate comprising a gate dielectric and a gate electrode;    forming sidewall insulators coupled to said gate;    implanting a source extension region and a drain extension region into said semiconductor substrate, said source extension region and said drain extension region comprising arsenic atoms;    implanting a halo region into said semiconductor substrate, said halo region comprising boron atoms;    implanting impurity atoms into said semiconductor substrate;    forming source/drain spacers coupled to said sidewall insulators;    implanting a source and a drain into said semiconductor substrate;    heating said semiconductor wafer to diffuse said boron atoms; and    forming a source contact coupled to said source, a drain contact coupled to said drain, and a gate contact coupled to said gate.    
     
     
         10 . The method of  claim 9  wherein said impurity atoms comprise fluorine atoms.