Transistor assembly and method for the production thereof

Abstract

A transistor assembly with semiconductor material vertically introduced into micro holes ( 4 ) in a pliable a film laminate consisting of two plastic films ( 1, 3 ) with a metal layer ( 2 ) located therebetween. Said semiconductor material is provided with contacts ( 6, 7 ) by metalizing the top side and bottom side of the film laminate. The assembly is very strong by virtue of the fact that the film can be bent and stretched.

What is claimed is:  
     
         1 . A transistor arrangement, 
 characterized by the fact that semiconductor material is vertically introduced into micro holes ( 4 ) of a film laminate consisting of two plastic films ( 1 ,  3 ) with an intermediate metal layer ( 2 ), the semiconductor material being provided with contacts ( 6 ,  7 ) by metalization of the upper and lower surface of the film laminate.    
     
     
         2 . The transistor arrangement of  claim 1 , 
 characterized by the fact that    the film ( 1 ,  3 ) is a polymer film.    
     
     
         3 . The transistor arrangement of  claim 1 , 
 characterized by the fact that    the film ( 1 ,  3 ) is a polyester film.    
     
     
         4 . The transistor arrangement of  claim 3 , 
 characterized by the fact that    the film ( 1 ,  3 ) is a PET film.    
     
     
         5 . The transistor arrangement of one of the preceding claims, 
 characterized by the fact that    the film ( 1 ,  3 ) is of a thickness of 2 μm to 30 μm.    
     
     
         6 . The transistor arrangement of one of the preceding claims, 
 characterized by the fact that    the metal layer ( 2 ) consists of copper, aluminum or silver.    
     
     
         7 . The transistor arrangement of one of the preceding claims, 
 characterized by the fact that    the semiconductor material is copper thiocyanate (CuSCN).    
     
     
         8 . A method of fabricating a transistor arrangement, 
 characterized by the fact that    a metal layer is embedded between two plastic films, that ion trace channels are introduced into this laminate film by ion bombardment, that the film laminate is subsequently subjected to an etching treatment, that the ion trace channels etched to micro holes are filled with semiconductor material and that by metal coating source or drain contacts are formed on the upper and lower surface of the film laminate.    
     
     
         9 . The method of  claim 8 , 
 characterized by the fact that    the metal layer between the plastic films is subjected within the micro holes to a special etching treatment.    
     
     
         10 . The method of  claim 9 , 
 characterized by the fact that    for forming field effect transistors the micro holes are provided with an insulating layer.    
     
     
         11 . The method of  claim 8  or  9 , 
 characterized by the fact that  
 for forming field effect transistors the metal layer in the area of the micro holes is etched away to behind the diameter of the micro holes.  
 
     
     
         12 . The method of  claim 8  or  9 , 
 characterized by the fact that  
 for forming field effect transistors the metal layer in the area of the micro holes is electro-chemically oxidized.  
 
     
     
         13 . The method of one of  claims 8  to  12 , 
 characterized by the fact that  
 filling of the micro holes with semiconductor material is carried out by electrode deposition.  
 
     
     
         14 . The method of one of  claims 8  to  12 , 
 characterized by the fact that  
 filling of the micro holes with semiconductor material is carried out by precipitation in a chemical bath.  
 
     
     
         15 . The method of one of  claims 8  to  14 , 
 characterized by the fact that  
 the etching treatment of the ion trace channels results in the formation of micro holes of a diameter between 30 nm and 20 μm.  
 
     
     
         16 . The method of one of  claims 8  to  15 , 
 characterized by the fact that  
 the metal layer is applied to one surface of the plastic foil by vaporization or sputtering.  
 
     
     
         17 . The method of one of  claims 8  to  16 , 
 characterized by the fact that  
 the plastic foil provided with the metal layer and the second plastic film are adhesively connected to each other.  
 
     
     
         18 . The method of one of  claims 8  to  17 , 
 characterized by the fact that  
 the etching of the ion trace channels is carried out with a sodium hydroxide solution.  
 
     
     
         19 . The method of one of  claims 8  to  18 , 
 characterized by the fact that  
 the ion bombardment is carried out at an ion density of 10 7 /cm 2  to 10 9 /cm 2 .  
 
     
     
         20 . The method of one of  claims 8  to  19 , 
 characterized by the fact that  
 the ion bombardment is carried out at an energy of several 100 MeV.  
 
     
     
         21 . The method of one of  claims 8  to  20 , 
 characterized by the fact that  
 that prior to etching of the ion trace channels the film laminate is treated with a sensitizing agent.  
 
     
     
         22 . The method of one of  claims 8  to  21 , 
 characterized by the fact that  
 the prior to metal coating of its upper and lower surface the film laminate is masked.  
 
     
     
         23 . The method of one of  claims 8  to  22 , 
 characterized by the fact that  
 the film laminate is masked prior to ion bombardment.  
 
     
     
         24 . A transistor assembly, comprising: 
 a film laminate comprising at least first and second adhesively connected superposed layers of pliable film and a metal layer interposed therebetween, the film laminate being provided with a plurality of micro holes;    a semiconductor material provided in the micro holes; and    electrical contacts connected to the semiconductor material and comprising a metalization on at least one outer surface of the film laminate.    
     
     
         25 . The transistor assembly of  claim 24 , wherein micro holes are of a diameter between 30 nm and 20 μm.  
     
     
         26 . The transistor assembly of  claim 25 , wherein the pliable film is a polymeric film.  
     
     
         27 . The transistor assembly of  claim 26 , wherein the polymeric film is a polyester film.  
     
     
         28 . The transistor assembly of  claim 26 , wherein the polyester film is a polyethylene terephthalate film.  
     
     
         29 . The transistor assembly of  claim 24 , wherein the pliable film is of a thickness of between 2 μm and 30 μm.  
     
     
         30 . The transistor assembly of  claim 24 , wherein the metal layer consists of the group selected from copper, aluminum and silver.  
     
     
         31 . The transistor assembly of  claim 24 , wherein the semiconductor material is copper thiocyanate (CuSCN).  
     
     
         32 . A method of fabricating a transistor assembly, comprising the steps of: 
 providing a film laminate comprising first and second layers of pliable film with a metal layer therebetween;    subjecting the film laminate to ion bombardment to provide a plurality of ion trace channels therein;    etching the film laminate to an etching process to convert the ion trace channels to micro holes;    vertically introducing into the micro holes a semiconductor material; and    metal coating at least one of the outer surfaces of the film laminate to provide at least one electrical contact connected to the semiconductor material.    
     
     
         33 . The method of  claim 32 , further comprising the step of subjecting the metal layer between the layers of pliable film to an etching process within the micro holes.  
     
     
         34 . The method of  claim 33 , further comprising the step of lining the micro holes with an insulating layer to form a field effect transistor.  
     
     
         35 . The method of  claim 34 , further comprising the step of etching away the metal layer in the area of the micro holes beyond the diameter of the micro holes to form a field effect transistor.  
     
     
         36 . The method of  claim 33 , further comprising the step of electro-chemically oxidizing the metal layer in the area of the micro holes to form a field effect transistor.  
     
     
         37 . The method of  claim 32 , wherein the step of introducing the semiconductor material is carried out by electrode deposition.  
     
     
         38 . The method of  claim 32 , wherein the step of introducing the semiconductor material is carried out by precipitation in a chemical bath.  
     
     
         39 . The method of  claim 32 , wherein the metal layer is applied to a surface of one plastic film by one of vapor deposition and sputtering.  
     
     
         40 . The method of  claim 39 , further comprising the step of adhesively connecting the pliable film with the metal layer thereon and the other pliable film by adhesion.  
     
     
         41 . The method of  claim 32 , wherein the step of etching for converting the ion trace channels to micro holes is carried out in a solution of sodium hydroxide.  
     
     
         42 . The method of  claim 32 , wherein the step of ion bombardment is carried out at a density of 10 7 /cm 2  to  10   9 /cm 2 .  
     
     
         43 . The method of  claim 32 , wherein the step of ion bombardment is carried out at a power of several 100 MeV.  
     
     
         44 . The method of  claim 40 , further comprising the step of subjecting the film laminate to a sensitizing agent prior to etching.  
     
     
         45 . The method of  claim 32 , further comprising the step of masking the film laminate prior to metal coating.  
     
     
         46 . The method of  claim 32 , further comprising the step of masking the film laminate prior to ion bombardment.