Can microcontroller that permits concurrent access to different segments of a common memory by both the processor core and the DMA engine thereof

Abstract

A CAN microcontroller that supports a plurality of message objects, including a processor core that runs CAN applications, and a CAN/CAL module that processes incoming messages, and a data memory. The data memory includes a first memory segment that provides a plurality of message buffers associated with respective ones of the message objects, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects. The memory-mapped registers for each message object contain respective command/control fields for configuration and setup of that message object. The CAN microcontroller further includes a memory interface unit that permits the processor core and the CAN/CAL module to concurrently access a different respective one of the first and second memory segments, and that arbitrates access to the same one of the first and second memory segments when the processor core and the CAN/CAL module request concurrent access to the same one of the first and second memory segments. In a second embodiment, the data memory includes a first memory space that is located on an integrated circuit chip on which the CAN microcontroller and the CAN/CAL module are incorporated, and a second memory space that is located off the integrated circuit chip. The first memory space includes a first memory segment that provides at least a portion of a message buffer memory space, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects. With this second embodiment, the CAN microcontroller further includes a memory interface unit that permits the processor core and the CAN/CAL module to concurrently access a different respective one of the first and second memory spaces, that permits the processor core and the CAN/CAL module to concurrently access a different respective one of the first and second memory segments, and that arbitrates access to the second memory space and that arbitrates access to the same one of the first and second memory segments when the processor core and the CAN/CAL module request concurrent access to the second memory space or to the same one of the first and second memory segments.

1 - 20  (canceled).  
     
     
         21 . A microcontroller that supports a plurality of message objects, comprising: 
 a processor core that runs applications;    a module that processes incoming messages;    data memory including a first memory segment that provides a plurality of message buffers associated with respective ones of the message objects, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects, the memory-mapped registers for each message object containing respective command/control fields for configuration and setup of that message object; and,    a memory interface unit that permits the processor core and the module to concurrently access a different respective one of the first and second memory segments, and that arbitrates access to the same one of the first and second memory segments when the processor core and the module request concurrent access to the same one of the first and second memory segments.    
     
     
         22 . The microcontroller as set forth in  claim 21 , wherein the incoming messages include multi-frame, fragmented messages, and the module automatically assembles the multi-frame, fragmented messages.  
     
     
         23 . The microcontroller as set forth in  claim 21 , wherein the module includes the memory-mapped registers.  
     
     
         24 . The microcontroller as set forth in  claim 21 , wherein the processor core, the module, and the memory interface unit are contained on a single integrated circuit chip.  
     
     
         25 . The microcontroller as set forth in  claim 24 , wherein the first and second memory segments are contained on the integrated circuit chip.  
     
     
         26 . The microcontroller as set forth in  claim 24 , wherein the memory interface unit includes two independent arbiters.  
     
     
         27 . The microcontroller as set forth in  claim 21 , wherein the memory interface unit arbitrates access according to an alternate winner policy, wherein a previous loser is designated a current winner.  
     
     
         28 . A microcontroller that supports a plurality of message objects, comprising: 
 a processor core that runs applications;    a module that processes incoming messages, wherein the processor core and the module are contained on a single integrated circuit chip;    data memory including a first memory space that is located on the integrated circuit chip and a second memory space that is located off the integrated circuit chip, the first memory space including a first memory segment that provides at least a portion of a message buffer memory space that includes a plurality of message buffers associated with respective ones of the message objects, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects, the memory-mapped registers for each message object containing respective command/control fields for configuration and setup of that message object; and,    a memory interface unit that permits the processor core and the module to concurrently access a different respective one of the first and second memory spaces, that permits the processor core and the module to concurrently access a different respective one of the first and second memory segments, and that arbitrates access to the second memory space and that arbitrates access to the same one of the first and second memory segments when the processor core and the module request concurrent access to the second memory space or to the same one of the first and second memory segments.    
     
     
         29 . The microcontroller as set forth in  claim 28 , wherein the incoming messages include multi-frame, fragmented messages, and the module automatically assembles the multi-frame, fragmented messages.  
     
     
         30 . The microcontroller as set forth in  claim 28 , wherein the module includes the memory-mapped registers.  
     
     
         31 . The microcontroller as set forth in  claim 28 , wherein the memory interface unit is contained on the single integrated circuit chip.  
     
     
         32 . The microcontroller as set forth in  claim 28 , wherein the second memory space provides at least a portion of the message buffer memory space.  
     
     
         33 . The microcontroller as set forth in  claim 28 , wherein the memory interface unit includes two independent arbiters dedicated to a respective one of the first and second memory spaces.  
     
     
         34 . The microcontroller as set forth in  claim 28 , wherein the memory interface unit arbitrates access according to an alternate winner policy, wherein a previous loser is designated a current winner.  
     
     
         35 . A method for operating a microcontroller that supports a plurality of message objects, the CAN microcontroller including a processor core that runs applications, a module that processes incoming messages, and a data memory including a first memory space that is located on the integrated circuit chip and a second memory space that is located off the integrated circuit chip, the first memory space including a first memory segment that provides at least a portion of a message buffer memory space that includes a plurality of message buffers associated with respective ones of the message objects, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects, the memory-mapped registers for each message object containing respective command/control fields for configuration and setup of that message object, the method comprising: 
 permitting the processor core and the module to concurrently access a different respective one of the first and second memory segments; and,    arbitrating access to the same one of the first and second memory segments when the processor core and the module request concurrent access to the same one of the first and second memory segments.    
     
     
         36 . The method as set forth in  claim 35 , wherein the arbitrating access step is performed in accordance with an alternate winner policy, wherein a previous loser is designated a current winner.  
     
     
         37 . The method as set forth in  claim 36 , wherein the arbitrating step is performed by a memory interface unit contained in the microcontroller.  
     
     
         38 . A method for operating a microcontroller that supports a plurality of message objects, the microcontroller including a processor core that runs applications, a module that processes incoming messages, and a data memory including a first memory space that is located on an integrated circuit chip on which the microcontroller and the module are incorporated, and a second memory space that is located off the integrated circuit chip, the first memory space including a first memory segment that provides at least a portion of a message buffer memory space that includes a plurality of message buffers associated with respective ones of the message objects, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects, the memory-mapped registers for each message object containing respective command/control fields for configuration and setup of that message object, the method comprising: 
 permitting the processor core and the module to concurrently access a different respective one of the first and second memory spaces;    permitting the processor core and the module to concurrently access a different respective one of the first and second memory segments;    arbitrating access to the second memory space when the processor core and the module request concurrent access to the second memory space; and,    arbitrating access to the same one of the first and second memory segments when the processor core and the CAN/CAL module request concurrent access to the first and second memory segments.    
     
     
         39 . The method as set forth in  claim 38 , wherein the arbitrating access step is performed in accordance with an alternate winner policy, wherein a previous loser is designated a current winner.  
     
     
         40 . The method as set forth in  claim 39 , wherein the arbitrating step is performed by a memory interface unit contained in the microcontroller.  
     
     
         41 . A bus station comprising a microcontroller that supports a plurality of message objects, comprising: 
 a processor core that runs applications;    a module that processes incoming messages;    data memory including a first memory segment that provides a plurality of message buffers associated with respective ones of the message objects, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects, the memory-mapped registers for each message object containing respective command/control fields for configuration and setup of that message object; and,    a memory interface unit that permits the processor core and the module to concurrently access a different respective one of the first and second memory segments, and that arbitrates access to the same one of the first and second memory segments when the processor core and the module request concurrent access to the same one of the first and second memory segments.    
     
     
         42 . A bus system comprising a microcontroller that supports a plurality of message objects, comprising: 
 a processor core that runs applications;    a module that processes incoming messages;    data memory including a first memory segment that provides a plurality of message buffers associated with respective ones of the message objects, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects, the memory-mapped registers for each message object containing respective command/control fields for configuration and setup of that message object; and,    a memory interface unit that permits the processor core and the module to concurrently access a different respective one of the first and second memory segments, and that arbitrates access to the same one of the first and second memory segments when the processor core and the module request concurrent access to the same one of the first and second memory segments.