Semiconductor device employing a method for forming a pattern using a crystal structure of a crystalline material

Abstract

The present invention relates generally to a semiconductor device, and in particular, to a semiconductor device employing a method for forming a pattern for the formation of quantum dots or wires with 1˜50 nm dimension using the atomic array of a single or a poly crystalline material. The electron beam lithography method in accordance with the present invention uses the phase contrast atomic image of a single or a poly crystalline material itself.

1 - 12 . (canceled)  
     
     
         13 . A semiconductor device, comprising: 
 a semiconductor substrate,    a source region located in said semiconductor substrate;    a drain region spaced apart from said source region and located in said semiconductor substrate;    a quantum dot layer formed by patterning a gate layer on a semiconductor substrate region which is located between said source and drain region wherein said patterning comprises a method for forming a pattern using a crystal structure of a single or a poly crystalline material, comprising the steps of:    locating said material having a crystal structure in a chamber;    radiating an electron beam to said material in said chamber;    forming a pattern from a lattice image of said material formed as a result of interference between diffracted beam and transmitted beam passed through said material on the surface of an electron beam resist on said gate layer.    
     
     
         14 . The semiconductor device of  claim 13 , wherein said material having a crystal structure has a thickness of a few tens of nanometer.  
     
     
         15 . The semiconductor device of  claim 13 , wherein a gate oxide film exists between said quantum dot layer and said semiconductor substrate.  
     
     
         16 . The semiconductor device of  claim 13 , wherein a control oxide layer is deposited on said quantum dot layer.  
     
     
         17 . The semiconductor device of  claim 13 , wherein said gate layer is formed of an amorphous Si.  
     
     
         18 . The semiconductor device of  claim 16 , wherein a polycrystalline Si layer is deposited on said control oxide layer.  
     
     
         19 . A semiconductor device, comprising: 
 a semiconductor substrate,    a source region located in said semiconductor substrate;    a drain region spaced apart from said source region and located in said semiconductor substrate;    a quantum dot layer formed by patterning a gate layer on a semiconductor substrate region which is located between said source and drain region wherein said patterning comprises an electron beam lithography method for forming a pattern using a crystal structure of a single or a poly crystalline material, comprising the steps of:    providing a film of electron beam resist on said gate layer;    irradiating an electron beam to said material in a chamber;    forming a pattern from a lattice image of said material formed as a result of interference between a diffracted beam and a transmitted beam passed through said material on said film of electron beam resist on said gate layer.    
     
     
         20 . The semiconductor device of  claim 19 , wherein said material having a crystal structure has a thickness of a few tens of nanometer.  
     
     
         21 . The semiconductor device of  claim 19 , wherein said lattice image of material is formed by a method of the phase contrast imaging.  
     
     
         22 . The semiconductor device of  claim 19 , wherein said material having a crystal structure is Si.  
     
     
         23 . The semiconductor device of  claim 19 , wherein said gate layer is formed of an amorphous Si.  
     
     
         24 . The semiconductor device of  claim 19 , wherein a gate oxide film exists between said quantum dot layer and said semiconductor substrate.  
     
     
         25 . The semiconductor device of  claim 19 , wherein a control oxide layer exists on said quantum dot layer.  
     
     
         26 . The semiconductor device of  claim 25 , wherein a polycrystalline Si layer is deposited on said control oxide layer.  
     
     
         27 . A semiconductor device, comprising: 
 a semiconductor substrate;    a source region located in semiconductor substrate;    a drain region spaced apart from said source region and located in said semiconductor substrate;    a quantum dot layer formed by patterning a gate layer on a semiconductor substrate region which is located between said source and drain region wherein said patterning comprises an electron beam lithography method for forming a pattern using a crystal structure of a single or a poly crystalline material, comprising the steps of:    providing a film of electron beam resist on said gate layer;    irradiating an electron beam to said material in a chamber;    forming a pattern from a lattice image of said material formed as a result of interference between a diffracted beam and a transmitted beam passed through said material on said film of electron beam resist on said gate layer,    patterning said film of electron beam resist on said gate layer.    
     
     
         28 . The semiconductor device of  claim 27 , wherein said lattice image of material is formed by a method of the phase contrast imaging.  
     
     
         29 . The semiconductor device of  claim 27 , wherein said material having a crystal structure has a thickness of a few tens of nanometer.  
     
     
         30 . The semiconductor device of  claim 27 , wherein said electron beam lithography method further comprises passing said diffracted beam and said transmitted beam through an aperture prior to said step of forming said pattern.  
     
     
         31 . The semiconductor device of  claim 27 , wherein said gate layer is formed of an amorphous Si.  
     
     
         32 . The semiconductor device of  claim 27 , wherein a gate oxide exists between said quantum layer and said semiconductor substrate.