Semiconductor device and ic card

Abstract

Wiring lines for the supply of a voltage to feed a drive voltage to an integrated circuit formed in a semiconductor chip are disposed so as to cover a main surface of the semiconductor chip, so that, if the wiring lines are removed for the purpose of analyzing information stored in the semiconductor chip, the integrated circuit does not operate and it is impossible to analyze the information. Further, there is provided a processing detector circuit for detecting that the wiring lines have been tampered with. When the processing detector circuit detects a change in the state of the wiring lines, the integrated circuit is reset. Thus, it is possible to improve the security of information stored on the card.

1 . A semiconductor device comprising: 
 (a) a first element formed over a main surface of a semiconductor chip and contributing to the storage of information;    (b) a second element formed over the main surface of the semiconductor chip;    (c) a first area formed over the main surface of the semiconductor chip and divided into a plurality of second areas;    (d) a desired signal line formed in the first area; and    (e) wiring lines for supply voltage contributing to the actuation of the first and second elements, the wiring lines for supply voltage being disposed respectively in the plural second areas in a layer which overlies the desired signal line so as not to permit the analysis of information unless they are cut off or removed, and being formed so as to be different in shape.    
     
     
         2 . A semiconductor device comprising: 
 (a) a first element formed over a main surface of a semiconductor chip and contributing to the storage of information;    (b) a second element formed over the main surface of the semiconductor chip;    (c) a first area disposed over the main surface of the semiconductor chip and divided into a plurality of second areas so as to cover the main surface of the semiconductor chip;    (d) a desired signal line formed in at least one of the plural second areas; and    (e) a wiring line for supply voltage contributing to the actuation of the first and second elements and disposed respectively in the plural second areas in a layer which overlies the desired signal line, the wiring lines for supply voltage being formed so as to be different in shape.    
     
     
         3 . A semiconductor device comprising: 
 (a) a first element formed over a main surface of a semiconductor chip and contributing to the storage of information;    (b) a second element formed over the main surface of the semiconductor chip;    (c) a first area disposed over the main surface of the semiconductor chip and divided into a plurality of second areas;    (d) desired signal line formed in the first area; and    (e) wiring lines for supply voltage contributing to the actuation of the first and second elements and partially respectively in the plural second areas so as to cover the desired signal line in a layer which overlies the desired signal line, and being formed so as to be different in shape.    
     
     
         4 . A semiconductor device according to any of  claims 1  to  3 , wherein, when the wiring line for supply voltage is cut off or removed, a supply voltage is not fed to the first or the second element and a circuit does not operate.  
     
     
         5 . A semiconductor device according to any of  claims 1  to  3 , 
 wherein the wiring line for supply voltage comprises a wiring line for supply voltage on a high potential side which supplies a relatively high supply voltage and a wiring line for supply voltage on a low potential side which supplies a relatively low supply voltage, and  
 wherein the wiring line for supply voltage on a high potential side and the wiring line for supply voltage on a low potential side are planarly deviated from each other in such a manner that one is interposed in gaps formed in the other and the other is interposed in gaps formed in the one.  
 
     
     
         6 . A semiconductor device according to any of  claims 1  to  3 , 
 wherein the wiring line for supply voltage comprises a wiring line for supply voltage on a high potential side which supplies a relatively high supply voltage and a wiring line for supply voltage on a low potential side which supplies a relatively low supply voltage, and  
 wherein the wiring line for supply voltage on a high potential side and the wiring line for supply voltage on a low potential side are formed in the shape of comb teeth and arranged planarly so that the respective teeth are in mesh with each other.  
 
     
     
         7 . A semiconductor device according to any of  claims 1  to  3 , 
 wherein the wiring line for supply voltage comprises a wiring line for supply voltage on a high potential side which supplies a relatively high supply voltage and a wiring line on a low potential side which supplies a relatively low supply voltage, and  
 wherein the wiring line for supply voltage on a high potential side and the wiring line for supply voltage on a low potential side are formed in a lattice shape and arranged planarly so that one is interposed in gaps formed in the other and the other is interposed in gaps formed in the one.  
 
     
     
         8 . A semiconductor device according to any of  claims 1  to  3 , 
 wherein the wiring line for supply voltage comprises a wiring line for supply voltage on a high potential side which supplies a relatively high supply voltage and a wiring line for supply voltage on a low potential side which supplies a relatively low supply voltage, and  
 wherein the wiring line for supply voltage on the high potential side and the wiring line for supply voltage on the low potential side are solid wiring lines.  
 
     
     
         9 . A semiconductor device comprising: 
 (a) a first element formed over a main surface of a semiconductor chip and contributing to the storage of information;    (b) a first area disposed over the main surface of the semiconductor chip and divided into a plurality of second areas;    (c) a desired signal line formed in the first area; and    (d) a detector circuits disposed respective in the plural second areas in a layer which overlies the desired signal line, the detector circuits, when first wiring lines formed so as to be different in shape are cut off, detecting it and make it impossible to analyze information stored in the first element.    
     
     
         10 . (canceled)  
     
     
         11 . A semiconductor device according to  claim 9 , wherein the first wiring line is a wiring line for supply voltage.  
     
     
         12 . A semiconductor device according to  claim 11 , wherein the wiring line for supply voltage comprises a wiring line for supply voltage on a high potential side which supplies a relatively high supply voltage and a wiring line for supply voltage on a low potential side which supplies a relatively low supply voltage.  
     
     
         13 . A semiconductor device according to  claim 11 , wherein the wiring line for supply voltage is constituted by a single wiring line which is disposed in a predetermined shape so as to cover the desired signal line.  
     
     
         14 . A semiconductor device according to  claim 11 , wherein the wiring line for supply voltage is constituted by a single wiring line in such a manner that, when the single wiring line is cut off, the cut-off wiring portions are completely isolated from each other.  
     
     
         15 . A semiconductor device according to  claim 9 , wherein the detector circuit is dispersed plurally within the main surface of the semiconductor chip.  
     
     
         16 . A semiconductor device according to  claim 15 , wherein the detector circuit is disposed in a circuit block area of the main surface of the semiconductor chip.  
     
     
         17 . A semiconductor device according to  claim 15  or  claim 16 , wherein the detector circuit is disposed in a wiring area of the main surface of the semiconductor chip.  
     
     
         18 . A semiconductor device according to any of  claims 12  to  14 , wherein the wiring line for supply voltage is different from a wiring line for supply voltage which supplies a supply voltage for actuating the detector circuits.  
     
     
         19 . A semiconductor device according to  claim 9 , wherein an input wiring line of a predetermined one of said plural detector circuits is used as a wiring line for supply voltage in the other detector circuit.  
     
     
         20 . A semiconductor device comprising: 
 (a) a first element formed over a main surface of a semiconductor chip and contributing to the storage of information;    (b) a second element formed over the main surface of the semiconductor chip;    (c) a first area disposed over the main surface of the semiconductor chip and divided into a plurality of second areas so as to cover the main surface of the semiconductor chip; and    (d) a desired signal line formed in at least one of the plural second areas; and    (e) wiring lines for supply voltage which contribute to actuating the first and second elements, the wiring lines for supply voltage being each constituted by a single wiring line in such a manner that, when the single wiring line is cut off, the cut-off wiring portions are completely isolated from each other so as not to actuate the first and second elements, the wiring line for supply voltage being disposed respectively in the plural second areas in a layer which overlies the desired signal line, and being formed so as to be different in shape.    
     
     
         21 . An IC card comprising: 
 (a) a first element formed over a main surface of a semiconductor chip and contributing to the storage of information;    (b) a second element formed over the main surface of the semiconductor chip;    (c) a first area disposed over the main surface of the semiconductor chip and divided into a Plurality of second areas;    (d) a desired signal line formed in the first area;    (e) wiring lines for supply voltage which contributes to actuating the first and second elements, the wiring lines for supply voltage being disposed respectively in the plural second areas in a layer which overlies the desired signal line so as not to permit the analysis of information unless it is cut off or removed, and being formed so as to be different in shape;    (f) a package for sealing the semiconductor chip; and    (g) plate-like card body which receives the package within a groove.    
     
     
         22 . An IC card comprising: 
 (a) a first element formed over a main surface of a semiconductor chip and contributing to the storage of information;    (b) a second element formed over the main surface of the semiconductor chip;    (c) a first area disposed over the main surface of the semiconductor chip and divided into a plurality of second areas so as to cover the main surface of the semiconductor chip;    (d) a desired signal line formed in at least one of the plural second areas;    (e) wiring lines for supply voltage which contributes to actuating the first and second elements, the wiring lines for supply voltage being disposed respectively in the plural second areas in a layer which overlies the desired signal line, and being formed so as to be different in shape;    (f) a package for sealing the semiconductor chip; and    (g) plate-like card body which receives the package within a groove.    
     
     
         23 . An IC card comprising: 
 (a) a first element formed over a main surface of a semiconductor chip and contributing to the storage of information;    (b) a second element formed over the main surface of the semiconductor chip;    (c) a first area disposed over the main surface of the semiconductor chip and divided into a Plurality of second areas;    (d) a desired signal line formed in the first area;    (e) a wiring lines for supply voltage which contributes to actuating the first and second elements, the wiring line for supply voltage being partially disposed respectively in the plural second areas so as to cover the desired signal line in a layer which overlies the desired signal line, and being formed so as to be different in shape;    (f) a package for sealing the semiconductor chip; and    (g) a plate-like card body which receives the package within a groove.    
     
     
         24 . An IC card comprising: 
 (a) a first element formed over a main surface of a semiconductor chip and contributing to the storage of information;    (b) a second element formed over the main surface of the semiconductor chip;    (c) a first area disposed over the main surface of the semiconductor chip and divided into a plurality of second area;    (d) a desired signal line formed in the first area    (e) wiring lines for supply voltage which contributes to actuating the first and second elements, the wiring lines for supply voltage being formed respectively in the plural second areas in a layer which overlies the designed signal line, the wiring lines for supply voltage being formed so as to be different in shape, wherein when the wiring line for supply voltage is cut off or removed, a supply voltage is not fed to the first or the second element and a circuit does not operate.    
     
     
         25 . An IC card according to any of claims  21 ,  22 ,  23 , and  24 , 
 wherein the wiring line for supply voltage comprises a wiring line for supply voltage on a high potential side which supplies a relatively high supply voltage and a wiring line for supply voltage on a low potential side which supplies a relatively low supply voltage, and    the wiring line for supply voltage on a high potential side and the wiring line for supply voltage on a low potential side are planarly deviated from each other in such a manner that one is interposed in gaps formed in the other and the other is interposed in gaps formed in the one.    
     
     
         26 . An IC card according to any of claims  21 ,  22 ,  23 , and  24   wherein the wiring line for supply voltage comprises a wiring line for supply voltage on a high potential side which supplies a relatively high supply voltage and a wiring line for supply voltage on a low potential side which supplies a relatively low supply voltage, and    wherein the wiring line for supply voltage on a high potential side and the wiring line for supply voltage on a low potential side are formed in the shape of comb teeth and arranged planarly so that the respective teeth are in mesh with each other.    
     
     
         27 . An IC card according to any of claims  21 ,  22 ,  23 , and  24   wherein the wiring line for supply voltage comprising a wiring line for supply voltage on a high potential side which supplies a relatively high supply voltage and a wiring line for supply voltage on a relatively low potential side which supplies a relatively low supply voltage, and    wherein the wiring line for supply voltage on a high potential side and the wiring line for supply voltage on a low potential side are formed in a lattice shape and arranged planarly so that one is interposed in gaps formed in the other and the other is interposed in gaps formed in the one.    
     
     
         28 . An IC card according to any of claims  21 ,  22 , and  23 , 
 wherein the wiring line for supply voltage comprises a wiring line for supply voltage on a high potential side which supplies a relatively high voltage and a wiring line for supply voltage on a low potential side which supplies a relatively low supply voltage, and    wherein the wiring line for supply voltage on a high potential side and the wiring line for supply voltage on a low potential side are solid wiring lines.    
     
     
         29 . An IC card comprising: 
 (a) a first element formed over a main surface of a semiconductor chip and contributing to the storage of information;    (b) a second element formed over the main surface of the semiconductor chip;    (c) a first area disposed over the main surface of the semiconductor chip and divided into a plurality of second areas;    (d) a desired signal line formed in the first area;    (e) detector circuits disposed respectively in the plural second areas in a layer overlying the desired signal line and detecting, when first wiring lines formed so as to be different in shape are cut off, it and makes it impossible to analyze information stored in the first element;    (f) a package for sealing the semiconductor chip; and    (g) a plate-like card body which receives the package within a groove.    
     
     
         30 . An IC card comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip and divided into a plurality of second areas;    (b) first wiring lines formed in the first area;    (c) a detector circuit for detecting a change in potential of the first wiring line;    (d) a package for sealing the semiconductor chip; and    (e) a plate-like card body which receives the package within a groove, 
 wherein the first wiring lines are disposed respectively in the plurally divided second areas and are formed so as to be different in shape.  
   
     
     
         31 . An IC card according to  claim 29  or  claim 30 , wherein the first wiring line is a wiring line for supply voltage.  
     
     
         32 . An IC card according to  claim 31 , wherein the wiring line for supply voltage comprises a wiring line for supply voltage on a high potential side which supplies a relatively high supply voltage and a wiring line for supply voltage on a low potential side which supplies a relatively low voltage.  
     
     
         33 . An IC card according to  claim 31 , wherein the wiring line for supply voltage is constituted by a single wiring line which is disposed in a predetermined shape so as to cover the desired signal line.  
     
     
         34 . An IC card according to  claim 31 , wherein the wiring line for supply voltage is constituted by a single wiring line in such a manner that, when the single wiring line is cut off, the cut-off wiring portions are completely isolated from each other.  
     
     
         35 . An IC card according to any of claims  29  and  30 , wherein the detector circuit is dispersed plurally within the main surface of the semiconductor chip.  
     
     
         36 . An IC card according to  claim 35 , wherein the detector circuit is disposed in a circuit block area of the main surface of the semiconductor chip.  
     
     
         37 . An IC card according to  claim 35 , wherein the detector circuit is disposed in a wiring area of the main surface of the semiconductor chip.  
     
     
         38 . An IC card according to  claim 31 , wherein the wiring line for supply voltage is different from a wiring line for supply voltage for actuating the detector circuits.  
     
     
         39 . An IC card according to any of claims  29  and  30 , wherein an input wiring line of a predetermined one of said plural detector circuits is used as a wiring line for supply voltage in the other detector circuit.  
     
     
         40 . An IC card comprising: 
 (a) a first element formed over a main surface of a semiconductor chip and contributing to the storage of information;    (b) a second element formed over the main surface of the semiconductor chip;    (c) a first area disposed over the main surface of the semiconductor chip and divided into a plurality of second areas so as to cover the main surface of the semiconductor chip;    (d) a desired signal line formed in at least one of the plural second areas;    (e) wiring lines for supply voltage which contributes to actuating the first and second elements, the wiring lines for supply voltage being each constituted by a single wiring line in such a manner that, when the single wiring line is cut off, the cut-off wiring portions are completely isolated from each other so as not to actuate the first and second elements, the wiring lines for supply voltage being disposed respectively in the plural second areas in a layer which overlies the desired signal line, and being formed so as to be different in shape;    (f) a package for sealing the semiconductor chip; and    (g) plate-like card body which receives the package within a groove.    
     
     
         41 . (canceled)  
     
     
         42 . (canceled)  
     
     
         43 . A semiconductor device comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip;    (b) a plurality of second areas formed by dividing the first area;    (c) first wiring lines disposed respectively in the second area; and    (d) a detector circuit for detecting a processing of one of the first wiring lines which is disposed in a predetermined one of the plural second areas.    
     
     
         44 . A semiconductor device according to  claim 43 , wherein a wiring line for supply voltage which contributes to actuating an integrated circuit formed in the semiconductor chip is disposed in a wiring layer different from a wiring layer in which the first wiring line is disposed, the wiring line for supply voltage being disposed in the first area so as to lie over the first wiring line planarly.  
     
     
         45 . A semiconductor device according to  claim 44 , wherein a pattern of the first wiring line is disposed in a planar position corresponding to a gap between adjacent portions of a pattern of the wiring line for supply voltage.  
     
     
         46 . A semiconductor device according to any of claims  43 ,  44 , and  45 , wherein said plural first wiring lines different in shape are disposed in the first area and in one and same wiring layer.  
     
     
         47 . A semiconductor device according to  claim 46 , wherein the first wiring lines different in shape are disposed in such a manner that a pattern of one of said first wiring lines is interposed in a gap between adjacent portions of a pattern of the other first wiring line.  
     
     
         48 . A semiconductor device according to any of claims  43 ,  44  and  45 , wherein the first area is divided into plural second areas and said plural first wiring lines are disposed in the second areas respectively, the first wiring lines being mutually different in shape.  
     
     
         49 . A semiconductor device according to any of claims  43 ,  44  and  45 , wherein the first area is divided into plural second areas and said plural first wiring lines are disposed in the divided second areas respectively in such a manner that first wiring line disposed in a predetermined one of the plural second areas and the first wiring line disposed in the other second area are different in shape.  
     
     
         50 . A semiconductor device according to any of claims  43 ,  44  and  45 , wherein the first area is divided into plural second areas and the first wiring line is disposed in a predetermined one of the plural second areas, while in the other second area is disposed a wiring line for supply voltage so as to cover the other second area, the wiring line for supply voltage contributing to actuating an integrated circuit formed in the semiconductor chip.  
     
     
         51 . A semiconductor device according to  claim 50 , wherein the first wiring line and the wiring line for supply voltage are disposed in one and same wiring layer.  
     
     
         52 . A semiconductor device according to any of claims  43 ,  44  and  45 , wherein said plural detector circuits are connected electrically to the first wiring line.  
     
     
         53 . A semiconductor device according to any of claims  43 ,  44  and  45 , wherein the detector circuit is disposed in an irregular position with respect to the position of the first wiring line to which the detector circuit is connected.  
     
     
         54 . A semiconductor device according to any of claims  43 ,  44  and  45 , wherein the wiring width and pitch of the first wiring line are set equal to those of a wiring line which constitutes an integrated circuit formed in the semiconductor chip.  
     
     
         55 . A semiconductor device according to any of claims  43 ,  44  and  45 , wherein the potential of the first wiring line is changed.  
     
     
         56 . A semiconductor device according to any of claims  43 ,  44  and  45 , wherein the potential of the first wiring line is changed irregularly.  
     
     
         57 . A semiconductor device according to any of claims  43 ,  44  and  45 , wherein a signal having a predetermined frequency is allowed to flow through the first wiring line and is detected by the detector circuit.  
     
     
         58 . A semiconductor device according to any of claims  43 ,  44  and  45 , wherein the first wiring line is disposed in a wiring layer overlying a desired signal line which constitutes an integrated circuit formed in the semiconductor chip.  
     
     
         59 . A semiconductor device comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip;    (b) a plurality of second areas formed by dividing the first area;    (c) a first wiring line disposed in a predetermined one of the plural second areas;    (d) a wiring line for supply voltage which contributes to actuating an integrated circuit formed in the semiconductor chip, the wiring line for supply voltage being disposed in the other of the plural second areas so as to cover the other second area, and being different in shape from the first wiring line; and    (e) a detector circuit for detecting a processing of the first wiring line.    
     
     
         60 . A semiconductor device comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip;    (b) a first wiring line disposed in the first area;    (c) a wiring line for supply voltage which contributes to actuating an integrated circuit formed in the semiconductor chip, and is disposed in a wiring layer different from a wiring layer in which the first wiring line is disposed, the wiring line for supply voltage being disposed in the first area so as to lie over the first wiring planarly, and being formed so as to be different in shape from the first wiring line; and    (d) a detector circuit for detecting a processing of the first wiring line.    
     
     
         61 . (canceled)  
     
     
         62 . (canceled)  
     
     
         63 . A semiconductor device comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip;    (b) a first wiring line disposed in the first area; and    (c) a detector circuit for detecting a processing of the first wiring line, 
 wherein said plural first wiring lines different in shape are disposed in different areas included in the first area.  
   
     
     
         64 . (canceled)  
     
     
         65 . (canceled)  
     
     
         66 . A semiconductor device comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip;    (b) a plurality of second areas formed by dividing the first area;    (c) first wiring lines disposed respectively for the plural second areas; and    (d) a detector circuit for detecting a processing of the first wiring lines, 
 wherein the detector circuit is disposed so as to be irregular in a positional relation thereof to the second areas having the first wiring lines to which the detector circuit is connected.  
   
     
     
         67 . A semiconductor device according to  claim 63 , wherein the wiring width and pitch of the first wiring lines are set equal to those of a wiring line which constitutes an integrated circuit formed over the semiconductor chip.  
     
     
         68 . A semiconductor device according to  claim 63 , wherein the potential of the first wiring lines is changed.  
     
     
         69 . A semiconductor device according to  claim 63 , wherein the potential of the first wiring line is changed irregularly.  
     
     
         70 . A semiconductor device comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip;    (b) a first wiring line disposed in the first area;    (c) a detector circuit for detecting a processing of the first wiring line, 
 wherein a signal having a predetermined frequency is allowed to flow through the first wiring line and is detected by the detector circuit.  
   
     
     
         71 . A semiconductor device comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip; and    (b) a first wiring line disposed in the first area, 
 wherein the first area is divided into a plurality of second areas, and said plural first wiring lines disposed respectively in the second areas are different in shape.  
   
     
     
         72 . A semiconductor device comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip;    (b) a first wiring line disposed in the first area; and    (c) a detector circuit for detecting a change in potential of the first wiring line, 
 wherein the first area is divided into a plurality of second areas, and said plural first wiring lines disposed respectively in the second areas are different in shape.  
   
     
     
         73 . A semiconductor device according to  claim 72 , wherein the detector circuit is disposed in such a manner that a positional relation thereof to the second area having the first wiring line to which the detector circuit is connected becomes irregular.  
     
     
         74 . A semiconductor device comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip;    (b) a plurality of second areas formed by dividing the first area;    (c) first wiring lines disposed respectively in the plural second areas; and    (d) a detector circuit for detecting a change of a predetermined one of the first wiring lines disposed in the second areas, 
 wherein the detector circuit is disposed in such a manner that a positional relation thereof to the second area having the first wiring line to which the detector circuit is connected becomes irregular.  
   
     
     
         75 . A semiconductor device comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip;    (b) a plurality of second areas formed by dividing the first area;    (c) first wiring lines disposed respectively in the plural second areas; and    (d) a detector circuit for detecting a change of a predetermined one of the first wiring lines disposed in the second areas, 
 wherein the first wiring lines disposed in the second area are different in shape, and  
 wherein the detector circuit is disposed in such a manner that a positional relation thereof to the second area having the predetermined first wiring line to which the detector circuit is connected becomes irregular.  
   
     
     
         76 . A semiconductor device according to any one of  claims 71  to  75 , wherein said plural detector circuits are provided for the first wiring lines.  
     
     
         77 . A semiconductor device according to any of  claims 71  to  75 , wherein the wiring width and pitch of the first wiring lines are set equal to those of a wiring line which constitutes an integrated circuit formed in the semiconductor chip.  
     
     
         78 . A semiconductor device according to any of  claims 72  to  75 , wherein the potential of the first wiring lines is changed.  
     
     
         79 . A semiconductor device according to any of  claims 72  to  75 , wherein the potential of the first wiring lines is changed irregularly.  
     
     
         80 . A semiconductor device according to any of  claims 72  to  75 , wherein a signal having a predetermined frequency is allowed to flow through the first wiring lines and is detected by the detector circuit.  
     
     
         81 . A semiconductor device comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip;    (b) a first wiring line having a shielding function and disposed in the first area; and    (c) a second wiring line having a shielding function and disposed in the first area, the second wiring line being formed in a layer different from a layer in which the first wiring line is formed.    
     
     
         82 . A semiconductor device comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip;    (b) a first wiring line having a shielding function and disposed in the first area; and    (c) a second wiring line having a shielding function and disposed in the first area, the second wiring line being formed in a layer different from a layer in which the first wiring line is formed, 
 wherein the first area is divided into a plurality of second areas, said second plural first wiring lines and second wiring lines are disposed in the second area and include those different in shape.  
   
     
     
         83 . A semiconductor device comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip;    (b) a plurality of second areas formed by dividing the first area;    (c) first wiring lines disposed respectively in the plural second areas;    (d) second wiring lines formed in a layer different from a layer in which the first wiring lines are formed, the second wiring lines being disposed respectively in the plural second areas; and    (e) a first detector circuit for detecting a change of a predetermined one of the first wiring lines disposed in the second areas, 
 wherein the first detector circuit is disposed in such a manner that a positional relation thereof to the second area having the predetermined wiring line to which the first detector circuit is connected becomes irregular.  
   
     
     
         84 . A semiconductor device comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip;    (b) a plurality of second areas formed by dividing the first area;    (c) first wiring lines disposed respectively in the plural second areas;    (d) second wiring lines formed in a layer different from a layer in which the first wiring lines are formed, the second wiring lines being disposed respectively in the plural second areas; and    (e) a first detector circuit for detecting a change of a predetermined one of the first wiring lines disposed respectively in the second areas, 
 wherein the first and second wiring lines disposed in the second areas are different in shape, and the first detector circuit is disposed in such a manner that a positional relation thereof to the second area having the predetermined first wiring line to which the first detector circuit is connected becomes irregular.  
   
     
     
         85 . A semiconductor device according to any of  claims 81  to  84 , wherein a second detector circuit for detecting a change of a predetermined one of the second wiring lines disposed respectively in the second areas is formed in the predetermined second wiring line.  
     
     
         86 . A semiconductor device according to any of claims  83  and  84 , wherein the first detector circuit is disposed in such a manner that a positional relation thereof to the second area having the first wiring line to which the first detector circuit is connected becomes irregular.  
     
     
         87 . A semiconductor device according to any of  claims 81  to  84 , wherein said plural first detector circuits are connected electrically to the first wiring lines.  
     
     
         88 . A semiconductor device according to any of  claims 81  to  84 , wherein at least one of the first and second wiring lines is wiring line for supply voltage to feed a voltage to an integrated circuit formed in the semiconductor chip.  
     
     
         89 . A semiconductor device comprising: 
 (a) a first area disposed over a main surface of a semiconductor chip;    (b) a first wiring line disposed in the first area; and    (c) a detector circuit for detecting a processing of the first wiring line, 
 wherein said plural first wiring lines different in shape are disposed in a mixed state within one and same area included in the first area, and  
 wherein the detector circuit is disposed in such a manner that a positional relation thereof to the first wiring line to which the detector circuit is connected becomes irregular.