Memory access interface for a micro-controller system with address/data multiplexing bus

Abstract

A memory access interface for connecting a memory to a micro-controller having an address/data multiplexing bus and a microprocessor is proposed. The memory access interface includes an address latch, a multiplexer, and a data buffer. The address latch latches and outputs the lower-bit address signal on the address/data multiplexing bus of the micro-controller when an address-latch-enable signal is enabled. The multiplexer receives the lower-bit address signal latched by the address latch, a higher-bit address signal outputted from the micro-controller, and an address signal outputted from the microprocessor and selectively outputs the address signal of the micro-controller or the address signal of the microprocessor as the address signal of the memory according to a first control signal. The data buffer transmits the signal of the data bus of the memory to the address/data multiplexing bus of the micro-controller during a data cycle of the micro-controller, and maintains a high impedance state during an address cycle of the micro-controller.

What is claimed is:  
     
         1 . A memory access interface for connecting a memory to a micro-controller and a first circuitry, the micro-controller being capable of transmitting a first group address signals and a second group address signals, the micro-controller being capable of transmitting the first group address signals or accessing data signals via an address/data bus, the memory access interface comprising: 
 an address holder for receiving the first group address signals on the address/data multiplexing bus and a first enable signal outputted from the micro-controller, and outputting the first group address signals when the first enable signal is enabled; and    a multiplexer for receiving the first group address signals outputted from the address holder, the second group address signals outputted from the micro-controller, and third address signals outputted from the first circuitry, the multiplexer being controlled by a first control signal of the micro-controller for selectively outputting the first and second group address signals or outputting the third address signals to the memory;    wherein the micro-controller can access the data of the memory during a data cycle of the micro-controller and the first circuitry can access the data of the memory during an address cycle of the micro-controller.    
     
     
         2 . The memory access interface according to  claim 1 , further comprising a data buffer for transmitting the data signals from the memory to the address/data bus of the micro-controller during the data cycle of the micro-controller, and for maintaining a high impedance state during the address cycle of the micro-controller, the data buffer being controlled by a second control signal of the micro-controller.  
     
     
         3 . A memory access method for controlling the access among a memory, a micro-controller and a first device, the memory access method comprising the steps of: 
 the micro-controller outputting a first address signal during an address cycle;    latching the first address signal as a latched address signal;    the first device outputting a second address signal to the memory and reading/writing data from/to the memory during the address cycle; and    outputting the latched address signal to the memory during a data cycle; and    reading/writing data from/to the memory during the data cycle.    
     
     
         4 . The memory access method according to  claim 3 , wherein the micro-controller further outputs a third address signal to the memory during the data cycle.