CMOS image sensor having double gate insulator therein and method for manufacturing the same

Abstract

The method for manufacturing a CMOS image sensor is employed to enhance an optical property and an electrical property structuring a double gate insulator in a pixel array and a single gate insulator in a logic circuit. The method includes steps of: preparing a semiconductor substrate incorporating therein a p-type epitaxial layer, wherein the semiconductor substrate is divided into two parts of which one part is defined as a pixel array and the other part is defined as a logic circuit; forming a first gate insulator on a top face of the p-type epitaxial layer; forming a mask on a top face of the first gate insulator in the pixel array; removing the first gate insulator in the logic circuit by using the mask; removing the mask in the pixel array; forming the second gate insulator on the top face of the first gate insulator in the pixel array and a top face of the p-type epitaxial layer in the logic circuit; and forming a photodiode and a plurality of transistors in the pixel array and at least one transistor in the logic circuit for processing a signal from the pixel array.

What is claimed is:  
     
         1 . A complementary metal oxide semiconductor (CMOS) image sensor, comprising: 
 a semiconductor substrate incorporating therein a p-type epitaxial layer formed by epitaxially growing up an upper portion of the semiconductor substrate;    a pixel array formed in one predetermined location of a semiconductor substrate, having a plurality of transistors and active areas therein; and    a logic circuit formed in the other predetermined location of the semiconductor substrate having active areas and at least one transistor for processing a signal from the pixel array, wherein a gate insulator of each transistor in the pixel array is thicker than a gate insulator of the transistor in the logic circuit.    
     
     
         2 . The CMOS image sensor as recited in  claim 1 , wherein the gate insulator of each transistor in the pixel array employs a double layer having a first and a second gate insulators and the gate insulator of the transistor in the logic circuit employs a single layer.  
     
     
         3 . The CMOS image sensor as recited in  claim 2 , wherein the first gate insulator has a thickness ranging from about 10 Å to about 40 Å and the second gate insulator has a thickness ranging from about 50 Å to about 60 Å.  
     
     
         4 . The CMOS image sensor as recited in  claim 1 , wherein the first gate insulator is silicon oxide (SiO 2 ) formed by thermally oxidizing the p-type epitaxial layer.  
     
     
         5 . A method for manufacturing a CMOS image sensor, the method comprising the steps of: 
 a) preparing a semiconductor substrate incorporating therein a p-type epitaxial layer therein, wherein the semiconductor substrate is divided into two parts of which one part is defined as a pixel array and the other part is defined as a logic circuit, the pixel array being isolated from the logic circuit by means of a field oxide region therebetween;    b) forming a first gate insulator on a top face of the p-type epitaxial layer;    c) forming a mask on a top face of the first gate insulator in the pixel array;    d) removing the first gate insulator in the logic circuit by using the mask;    e) removing the mask in the pixel array;    f) forming the second gate insulator on the top face of the first gate insulator in the pixel array and a top face of the p-type epitaxial layer in the logic circuit; and    g) forming a photodiode and a plurality of transistors in the pixel array and at least one transistor in the logic circuit for processing a signal from the pixel array.    
     
     
         6 . The method as recited in  claim 5 , wherein the first gate insulator has a thickness ranging from about 10 Å to about 40 Å and the second gate insulator has a thickness ranging from about 50 Å to about 60 Å.  
     
     
         7 . The method as recited in  claim 5 , wherein the step d) is carried out by means of a wet-etching process.  
     
     
         8 . The method as recited in  claim 7 , wherein the step d) is carried out by using an hydrofluoric acid (HF).  
     
     
         9 . The method as recited in  claim 7 , wherein the step d) is carried out by using a buffered oxide etchant (BOE).  
     
     
         10 . The method as recited in  claim 5 , wherein the step e) is carried out by using an O 2  plasma.  
     
     
         11 . The method as recited in  claim 5 , wherein the step e) is carried out by using a sulfuric acid (H 2 SO 4 ).  
     
     
         12 . The method as recited in  claim 5 , wherein the step e) is carried out by using a thinner.  
     
     
         13 . The method as recited in  claim 5 , wherein the first gate insulator is SiO 2  formed by thermally oxidizing the p-type epitaxial layer.