High voltage device and method for fabricating the same

Abstract

In a high voltage device and a method for fabricating the same, a semiconductor substrate includes first, second, and third regions, the second and third regions neighboring the first region with boundaries. The first and second drift regions are respectively formed in the second and third regions at a first depth. Insulating films are formed at a second depth less than the first depth, having a predetermined width respectively based on the boundary between the first and second regions and the boundary between the first and third regions. A channel ion injection region is formed with a variable depth along a surface of the semiconductor substrate belonging to the first region and the insulating films. A gate insulating film is formed on the channel ion injection region, partially overlapping the insulating films at both sides around the channel ion injection region. Source and drain regions are formed within the first and second drift regions, and a gate electrode is formed to surround the gate insulating film and to partially overlap the insulating films.

1 - 5 . (Canceled)  
     
     
         6 . A method for fabricating a high voltage device comprising the steps of: 
 forming first and second drift regions in a predetermined region of a semiconductor substrate;    forming drain and source regions within the first and second drift regions;    respectively forming trenches, having a predetermined width, in the first and second regions around a boundary between the first and second drift regions and in the semiconductor substrate between the source and drain regions;    exposing the semiconductor substrate;    forming a channel region within a surface of the exposed semiconductor substrate;    burying an insulating film in the trenches;    forming a gate insulating film on the semiconductor substrate containing the channel region and on the insulating film at both sides of the semiconductor substrate; and forming a gate electrode at an upper portion and both sides of the gate insulating film.    
     
     
         7 . The method of  claim 6 , wherein the trenches are respectively contacted with a boundary between the first drift region and the drain region and a boundary between the second drift region and the source region at the regions first sides.  
     
     
         8 . The method of  claim 6 , wherein the drain and source regions have a depth greater than that of the first and second drift regions.  
     
     
         9 . The method of  claim 6 , wherein the trenches have a depth less than that of the first and second drift regions and greater than that of the drain and source regions.  
     
     
         10 . The method of  claim 6 , further comprising the step of annealing the drain and source regions to enhance a junction after forming the regions.  
     
     
         11 . The method of  claim 6 , wherein the insulating film is selectively removed by an etch-back process leaving the insulating film in the trenches, after it is formed on an entire surface of the semiconductor substrate including the trenches.  
     
     
         12 . The method of  claim 6 , further comprising the steps of: 
 forming an interleaving insulating film on an entire surface of the semiconductor substrate after forming the gate electrode;    forming contact holes in the interleaving insulating film to partially expose the drain and source regions;    depositing a metal film on the entire surface of the semiconductor substrate including the contact holes; and    selectively removing the metal film to form contacts respectively contacted with the drain and source regions.