Method and interface for improved efficiency in performing bus-to-bus read data transfers

Abstract

A novel method and interface is provided for conducting read data transfers between an initiator device on a single-transaction bus and a target device on a split-transaction bus. Embodiments of the present invention permit the initiator device to “post” a read request for a specified amount of data from a specified address on the split-transaction bus to an interface that resides between the single-transaction bus and the split-transaction bus. The requested read data is then retrieved over the split-transaction bus and presented in a high-speed memory within the interface for direct access by the initiator device over the single-transaction bus. Latency is avoided because the initiator device is not required to wait for the emergence of the requested read data from the split-transaction bus but, instead, may continue to perform other activities on the single-transaction bus and then obtain the requested read data at a later time.

1 - 30 . (canceled)  
     
     
         31 . An interface for conducting read data transfers between a single-transaction bus and a split-transaction bus, comprising: 
 a command register that receives command information over the single-transaction bus;    read request generation logic that generates a read request and issues said read request over the split-transaction bus in response to the receipt of said command information by said command register;    a read data memory; and    read response routing logic that receives a response to said read request over the split-transaction bus and routes read data associated with said response to said read data memory for storage in said read data memory;    wherein said read data stored in said read data memory is accessible over the single-transaction bus.    
     
     
         32 . The interface of  claim 31 , wherein the single-transaction bus is a PCI bus.  
     
     
         33 . The interface of  claim 31 , wherein the split-transaction bus is a PCI-X bus.  
     
     
         34 . The interface of  claim 31 , wherein said command information specifies a quantity of requested data words, and wherein said read request generated by said read request generation logic includes said specified quantity of requested data words.  
     
     
         35 . The interface of  claim 31 , further comprising: 
 an address register that receives address information over the single-transaction bus;    wherein said read request generated by said read request generation logic includes said address information.    
     
     
         36 . The interface of  claim 31 , wherein said read request generated by said read request generation logic includes a unique source identifier assigned by said read request generation logic, wherein said unique source identifier is included in said response to said read request and is used by said read response routing logic to route said read data associated with said response to said read data memory.  
     
     
         37 . The interface of  claim 31 , wherein said read data memory comprises a random access memory.  
     
     
         38 . The interface of  claim 31 , further comprising: 
 write control logic that receives said read data associated with said response from said read response routing logic;    wherein said read data comprises one or more data words, and    wherein, for each data word within said read data, said write control logic generates a value corresponding to an address in said read data memory and stores said data word at said address in said read data memory.    
     
     
         39 . The interface of  claim 38 , further comprising: 
 a status register;    wherein said write control logic writes status information to said status register in response to receiving said read data associated with said response, said status information indicating that said read data associated with said response is available in said read data memory.    
     
     
         40 . The interface of  claim 38 , further comprising: 
 an interrupt line;    wherein said write control logic transmits an interrupt signal over said interrupt line in response to receiving said read data associated with said read response, said interrupt signal for indicating that said read data is available in said read data memory.    
     
     
         41 . A method for conducting read data transfers between a single-transaction bus and a split-transaction bus using an interface, comprising: 
 receiving command information over the single-transaction bus;    generating a read request in response to receiving said command information;    issuing said read request over the split-transaction bus;    receiving a response to said read request over the split-transaction bus; and    storing read data associated with said response;    wherein said stored read data is accessible over the single-transaction bus.    
     
     
         42 . The method of  claim 41 , wherein the single-transaction bus is a PCI bus.  
     
     
         43 . The method of  claim 41 , wherein the split-transaction bus is a PCI-X bus.  
     
     
         44 . The method of  claim 41 , further comprising: 
 receiving address information over the single-transaction bus;    wherein said generating a read request comprises generating a read request that includes said address information.    
     
     
         45 . The method of  claim 41 , wherein said command information specifies a quantity of requested data words, and said generating a read request comprises generating a read request that includes said specified quantity of requested data words.  
     
     
         46 . The method of  claim 41 , wherein said generating a read request comprises generating a read request that includes a unique source identifier, wherein said unique source identifier is included in said response received over said split transaction bus, and wherein said storing of said read data associated with said response comprises routing said read data to a memory based on said unique source identifier.  
     
     
         47 . The method of  claim 41 , wherein said storing of said read data associated with said response further comprises storing said read data in a memory.  
     
     
         48 . The method of  claim 47 , wherein said memory is a random access memory.  
     
     
         49 . The method of  claim 47 , wherein said read data comprises one or more data words and said storing of said read data in a memory comprises storing said one or more data words in said memory.  
     
     
         50 . The method of  claim 49 , wherein said storing one or more data words in said memory comprises, for each data word, generating a value corresponding to an address in said memory and storing said data word at said address in said memory.  
     
     
         51 . The method of  claim 41 , further comprising: 
 posting information to a status register in response to receiving said response.    
     
     
         52 . The method of  claim 41 , further comprising: 
 transmitting an interrupt signal over an interrupt line in response to receiving said response.    
     
     
         53 . An interface for conducting read data transfers between a single-transaction bus and a split-transaction bus, comprising: 
 a command register that receives command information over the single-transaction bus; and    read request generation logic that generates a read request and issues said read request over the split-transaction bus in response to the receipt of said command information by said command register.    
     
     
         54 . The interface of  claim 53 , wherein the single-transaction bus is a PCI bus.  
     
     
         55 . The interface of  claim 53 , wherein the split-transaction bus is a PCI-X bus.