Method for fabricating an integrated circuit with a transistor electrode

Abstract

Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

1 - 10 . (canceled).  
     
     
         11 . A method for fabricating an integrated circuit, the method comprising: 
 introducing a dopant of a first conductivity type into a semiconductor substrate to form a first well; and    forming a transistor T1 having first and second electrodes of the first conductivity type, the first electrode having at least a portion inside the first well,    wherein the first electrode is connected to a voltage for: (1) biasing the first well, and (2) coupling the voltage to the second electrode when the transistor is on.    
     
     
         12 . The method of  claim 11  further comprising: 
 introducing a dopant of a second conductivity type into the first well to form a second well inside the first well; and  
 forming one or more transistors T 2  having electrodes of the first conductivity type in the second well.  
 
     
     
         13 - 20 . (canceled).  
     
     
         21 . The method of  claim 11  wherein the voltage is between about 1.6V and about 2.5V.  
     
     
         22 . The method of  claim 11  wherein the dopant of a first conductivity type comprises phosphorous.  
     
     
         23 . The method of  claim 11  wherein transistor T1 further comprises a gate, wherein the gate receives an equalization signal.  
     
     
         24 . The method of  claim 12  wherein the dopant of a second conductivity type comprises boron.  
     
     
         25 . The method of  claim 12  wherein at least one of the electrodes of the first conductivity type in the second well is connected to a capacitor.  
     
     
         26 . The method of  claim 12  wherein at least one of the electrodes of the first conductivity type in the second well is connected to a bit line, wherein the bit line is further connected to the second electrode of transistor T1.  
     
     
         27 . The method of  claim 12  wherein the second well contains electrodes of a dynamic random access memory (DRAM) cell transistor.  
     
     
         28 . The method of  claim 12  further comprising: 
 introducing a dopant of the first conductivity type into the semiconductor substrate to form a third well of the first conductivity type, wherein the third well is for holding second-conductivity-type electrodes of one or more transistors, and wherein the third well does not overlap with the first well.  
 
     
     
         29 . The method of  claim 11 , wherein the second electrode is outside of the first well.  
     
     
         30 . The method of  claim 11 , wherein the transistor T1 has a channel region of the second conductivity type.  
     
     
         31 . The method of  claim 11 , wherein the first well is of the first conductivity type.  
     
     
         32 . The method of  claim 12 , wherein the second well is of the second conductivity type.  
     
     
         33 . A method for fabricating an integrated circuit, the method comprising: 
 introducing a dopant of a first conductivity type into a semiconductor substrate to form a first well of a first conductivity type; and    forming a transistor T1 having first and second electrodes of the first conductivity type, the first electrode having at least a portion inside the first well and a portion outside the first well,    wherein the first electrode is connected to a voltage for: (1) biasing the first well, and (2) coupling the voltage to the second electrode when the transistor is on.    
     
     
         34 . The method of  claim 33  wherein the portion of the first electrode outside the first well is in a region of a second conductivity type.