Floating point overflow and sign detection

Abstract

A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. Because the products being summed are in carry-save format, post-normalization is avoided within the adder feedback loop. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. Variable shifters are avoided in the adder mantissa path. A single mantissa shift of thirty-two bits is provided by a conditional shifter.

1 . An integrated circuit comprising: 
 a carry-save adder having first and second input nodes, and having an output node to produce a result in carry-save format, the result including a sum field and a carry field; and    an overflow detection circuit responsive to the sum field to detect an overflow condition in the carry-save adder.    
     
     
         2 . The integrated circuit of  claim 1  wherein the overflow detection circuit comprises an exclusive-or gate responsive to two most significant bits in the sum field.  
     
     
         3 . The integrated circuit of  claim 2  comprising: 
 a multiplier to produce a product from two floating point multiplicands having a first exponent weight;  
 a first floating point conversion unit coupled between the multiplier and the first node of the carry-save adder to convert the product from the first exponent weight to a converted product with a second exponent weight; and  
 a post-normalization circuit to convert the result of the carry-save adder to a floating point resultant having the first exponent weight.  
 
     
     
         4 . The integrated circuit of  claim 3  wherein the multiplier is configured to produce a product with an exponent weight of one.  
     
     
         5 . The integrated circuit of  claim 4  wherein the floating point conversion unit is configured to convert the product from an exponent weight of one to an exponent weight of thirty-two.  
     
     
         6 . The integrated circuit of  claim 3  wherein: 
 the product comprises an exponent having a least significant bit weight of one and a mantissa in carry-save format.  
 
     
     
         7 . The integrated circuit of  claim 6  wherein the floating point conversion unit is configured to shift a mantissa of the product by a number of bit positions equal to a value of the least significant five bits of the exponent of the product.  
     
     
         8 . The integrated circuit of  claim 3  wherein the converted product comprises a three bit exponent field having a least significant bit weight of thirty-two.  
     
     
         9 . The integrated circuit of  claim 8  wherein the converted product further comprises a fifty-seven bit mantissa field in carry-save format.  
     
     
         10 . The integrated circuit of  claim 3  wherein the post-normalization circuit is configured to be turned off while the carry-save adder is producing the result.  
     
     
         11 - 30 . (Canceled)