Semiconductor integrated circuit device and manufacturing method thereof

Abstract

Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of realizing the two-level gate insulator process for the DRAM without increasing the number of manufacturing steps and that of photomasks. After forming a gate electrode of a MISFET which constitutes a memory cell in a memory array region on a semiconductor substrate, the substrate is subjected to thermal treatment (re-oxidation process). At this time, since bird's beak of the thick gate insulating film formed below the sidewall portion of the gate electrode penetrates into the center of the gate electrode, a gate insulating film thicker than the gate insulating film before the re-oxidation process is formed just below the center of the gate electrode. Meanwhile, since the gate electrode in the peripheral circuit region has a gate length longer than that of the gate electrode in the memory array region, the thickness of the gate insulating film just below the center thereof is almost equal to that before the re-oxidation process.

1 . A semiconductor integrated circuit device, in which a plurality of first MISFETs each having a first gate electrode are formed in a first region of a main surface of a semiconductor substrate and a plurality of second MISFETs each having a second gate electrode are formed in a second region of the main surface of the semiconductor substrate, the second gate electrode having a gate length longer than that of the first gate electrode, 
 wherein thickness of a gate insulating film formed just below a center of the first gate electrode is larger than that of the gate insulating film formed just below a center of the second gate electrode, and    wherein thickness of the gate insulating film formed just below a sidewall portion of the first gate electrode is equal to that of the gate insulating film formed just below a sidewall portion of the second gate electrode.    
     
     
         2 . The semiconductor integrated circuit device according to  claim 1 , 
 wherein the first MISFET is a MISFET which constitutes a memory cell of a DRAM and the second MISFET is a MISFET which constitutes a peripheral circuit of the DRAM.    
     
     
         3 . The semiconductor integrated circuit device according to  claim 1 , 
 wherein the first and second gate electrodes have a laminate structure of a silicon film and a metal film.    
     
     
         4 . A semiconductor integrated circuit device, in which a first MISFET having a first gate insulating film and a first gate electrode is formed in a first region of a main surface of a semiconductor substrate and a second MISFET having a second gate insulating film and a second gate electrode is formed in a second region of the main surface of the semiconductor substrate, 
 wherein difference in thickness between the first gate insulating film locating just below the center of the first gate electrode and the first gate insulating film locating just below the sidewall portion of the first gate electrode is larger than difference in thickness between the second gate insulating film locating just below the center of the second gate electrode and the second gate insulating film locating just below the sidewall portion of the second gate electrode.    
     
     
         5 . The semiconductor integrated circuit device according to  claim 4 , 
 wherein the gate length of the second gate electrode is longer than that of the first gate electrode.    
     
     
         6 . The semiconductor integrated circuit device according to  claim 4 , 
 wherein thickness of the first gate insulating film formed just below the center of the first gate electrode is larger than that of the second gate insulating film formed just below the center of the second gate electrode, and    wherein thickness of the first gate insulating film formed just below the sidewall portion of the first gate electrode is equal to that of the second gate insulating film formed just below the sidewall portion of the second gate electrode.    
     
     
         7 . The semiconductor integrated circuit device according to  claim 4 , 
 wherein the first MISFET is a MISFET which constitutes a memory cell of a DRAM and the second MISFET is a MISFET which constitutes a peripheral circuit of the DRAM.    
     
     
         8 . The semiconductor integrated circuit device according to  claim 4 , 
 wherein the first and second gate electrodes have a laminate structure of a silicon film and a metal film.    
     
     
         9 . A semiconductor integrated circuit device, in which a first MISFET which constitutes a memory cell of a DRAM is formed in a first region of a main surface of a semiconductor substrate, a second MISFET which constitutes a part of a peripheral circuit of the DRAM is formed in a second region of the main surface of the semiconductor substrate, and a third MISFET which constitutes another part of the peripheral circuit of the DRAM is formed in a third region of the main surface of the semiconductor substrate, 
 wherein the thickness of a gate insulating film of the second MISFET is different from that of the gate insulating film of the third MISFET, and    wherein the thickness of the gate insulating film formed just below the center of the gate electrode of the first MISFET is larger than that of the gate insulating film formed just below the center of the gate electrode of the second MISFET and is also larger than that of the gate insulating film formed just below the center of the gate electrode of the third MISFET.    
     
     
         10 .- 16 . (Canceled)