Semiconductor device having a metal insulator metal capacitor

Abstract

A semiconductor has a MIM capacitor formed on the same level with a dual damascene Cu line. The semiconductor includes a first insulating interlayer with first contact holes, first metal lines formed in the first contact holes, and second and third insulating interlayers including the first metal lines. Second and third contact holes are formed in the second insulating interlayer to expose some region of the first metal lines, a trench is formed in the third insulating interlayer corresponding to the second and third contact holes, and a capacitor structure is formed in the second contact hole and the trench above the second contact hole. Second metal lines fill the second and third contact holes and the trenches above the second and third contact holes.

What is claimed is:  
     
         1 . A semiconductor device, which comprises: 
 a substrate:    a first insulating interlayer with a plurality of first contact holes over the substrate;    a plurality of first metal lines in the first contact holes;    second and third insulating interlayers sequentially formed over the substrate;    first metal lines in the second and third insulating interlayers;    second and third contact holes in the second insulating interlayer to expose a region of the first metal lines;    a trench in the third insulating interlayer, the trench corresponding to the second and third contact holes;    a first barrier metal film, a lower electrode of a capacitor, a dielectric film, and an upper electrode of the capacitor sequentially formed in the second contact holes and the trench above the second contact holes;    second barrier metal films respectively formed over the upper electrode of the capacitor of the second contact hole and the trench above the second contact hole, the third contact hole, and the trench above the third contact hole; and    second metal lines respectively formed over the second barrier metal films to fill the second and third contact holes and the trench above the second and third contact holes.    
     
     
         2 . The semiconductor device as claimed in  claim 1 , further comprising a diffusion barrier film formed over the first insulating interlayer.  
     
     
         3 . The semiconductor device as claimed in  claim 1 , further comprising an etching stopper formed over the second insulating interlayer.  
     
     
         4 . The semiconductor device as claimed in  claim 1 , further comprising a hard mask formed over the third insulating interlayer.  
     
     
         5 . The semiconductor device as claimed in  claim 1 , wherein each trench above the second and third contact holes has a greater width than widths of the second and third contact holes.  
     
     
         6 . The semiconductor device as claimed in  claim 1 , wherein the second contact hole, the trench above the second contact hole, the third contact hole, and the trench above the third contact hole are respectively formed in a dual damascene structure.  
     
     
         7 . The semiconductor device as claimed in  claim 1 , wherein the first and second metal lines comprise Cu.  
     
     
         8 . The semiconductor device as claimed in  claim 1 , wherein the second metal line is formed by combining a seed Cu film with an electroplated Cu film by a chemical and mechanical deposition or by combining a seed Cu film with an electroplated Cu film by an electroless method.  
     
     
         9 . The semiconductor device as claimed in  claim 1 , wherein the capacitor is in a same level as the second metal lines.