Random access memory architecture and serial interface with continuous packet handling capability

Abstract

A random access memory architecture and method of handling data packets is described. According to embodiments of the invention, an apparatus includes a first processing unit for receiving serial data input, a switch, and a plurality of serially connected random access memory devices. The random access memory devices transmit data packets and commands via write input ports, write output ports, read input ports, and read output ports. A method for routing data includes receiving serial data input in a first processing unit, generating a data packet based on the serial data input, transmitting the data packet to a first random access memory device via a write input port, decoding the data packet, determining whether to perform a command in the first random access memory device based on information in the data packet, and transmitting the data packet to a second random access memory device.

1 . A random access memory device comprising: 
 a random access memory module;    a write input port coupled to receive packets that include data and command information;    a decoder coupled to receive the packets from the write input port, and to access the random access memory module to perform the commands in the packets;    a read input port operable to receive bypass data; and    a read output port coupled to output the bypass data and data read from the random access memory module.    
     
     
         2 . The random access memory device of  claim 1  further comprising: 
 a write output port coupled to receive the packets from the write input port and to transmit the packets to another random access memory device.  
 
     
     
         3 . The random access memory device of  claim 2  further comprising: 
 a buffer coupled between the write input port and the write output port.  
 
     
     
         4 . The random access memory device of  claim 1 , further comprising: 
 a first multiplexer coupled between the read input port and the read output port; and    an idle signal coupled to the first multiplexer, wherein the first multiplexer is operable to output the idle signal when the read input port is not transmitting the bypass data to the read output port.    
     
     
         5 . The random access memory device of  claim 4  further comprising: 
 a second multiplexer coupled between the random access memory module and the read output port, the second multiplexer being further coupled to receive the output of the first multiplexer, wherein the second multiplexer is operable to output the output of the first multiplexer when read data is not being transmitted from the random access memory module.  
 
     
     
         6 . The random access memory device of  claim 5  further comprising: 
 an encoder coupled between the random access memory module and the second multiplexer.  
 
     
     
         7 . The random access memory device of  claim 5  further comprising: 
 a buffer coupled between the second multiplexer and the read output port.  
 
     
     
         8 . The random access memory device of  claim 2  further comprising: 
 a decoder coupled between the write input port and the write output port; and  
 an encoder coupled between the decoder and the write output port.  
 
     
     
         9 . The random access memory device of  claim 8 , further comprising: 
 a first multiplexer coupled between the read input port and the read output port; and    an idle signal coupled to the first multiplexer, wherein the first multiplexer is operable to output the idle signal when the read input port is not transmitting the bypass data to the read output port.    
     
     
         10 . The random access memory device of  claim 9  further comprising: 
 a second multiplexer coupled between the random access memory module and the read output port, the second multiplexer being further coupled to receive the output of the first multiplexer, wherein the second multiplexer is operable to output the output of the first multiplexer when read data is not being transmitted from the random access memory module.  
 
     
     
         11 . The random access memory device of  claim 10  further comprising: 
 an encoder coupled between the second multiplexer and the read output port.  
 
     
     
         12 . The random access memory device of  claim 9 , wherein the decoder includes a phase lock loop, the random access memory device further comprising: 
 a second decoder coupled between the read input port and the first multiplexer, wherein the second decoder includes a delay lock loop.    
     
     
         13 . An apparatus comprising: 
 a first processing unit operable to receive serial data input;    a switch operable to receive data to be transmitted;    a first random access memory device coupled to the first processing unit via a write input port, wherein the first processing unit is operable to transmit data packets to the first random access memory device via the write input port;    a second random access memory device coupled to the first random access memory device, the second random access memory device being further coupled to transmit the data to be transmitted to the switch.    
     
     
         14 . The apparatus of  claim 13  further comprising: 
 a plurality of random access memory devices coupled between the first random access memory device and the second random access memory device, wherein each random access memory device in the series includes:  
 a random access memory module;  
 a write input port coupled to receive packets that include data and commands, and to access the random access memory module to perform the commands in the packets;  
 a read input port operable to receive bypass data; and  
 a read output port coupled to output the bypass data and data read from the random access memory module.  
 
     
     
         15 . The apparatus of  claim 14  wherein each random access memory device further comprises: 
 a write output port coupled to receive the packets from the write input port and to transmit the packets to one of the other random access memory devices.  
 
     
     
         16 . The apparatus of  claim 15  wherein each of the plurality of random access memory devices is coupled in series with another of the plurality of random access memory devices.  
     
     
         17 . The apparatus of  claim 16  wherein the write output port of each of the plurality of random access memory devices is coupled to the write input port of next of the series of the plurality of random access memory devices.  
     
     
         18 . The apparatus of  claim 17  wherein the read output port of each of the plurality of random access memory devices is coupled to the read input port of next of the series of the plurality of random access memory devices.  
     
     
         19 . The apparatus of  claim 16  wherein each random access memory device is operable to generate an overflow signal to indicate to the next random access memory device in the series that the data to be written or read is a continuation from the previous random access memory device.  
     
     
         20 . The apparatus of  claim 19  wherein each random access memory device is operable to generate a command signal to indicate to the next random access memory device in the series that the continuation of data is to be written or read.  
     
     
         21 . The apparatus of  claim 16 , further comprising: 
 a plurality of serial data inputs; and    a plurality of the series of the random access memory devices, wherein each of the plurality of the series of the random access memory devices is dedicated to handling data from one of the plurality of serial data inputs.    
     
     
         22 . The apparatus of  claim 13  wherein random access memory devices are operable to decode the data packet and determine whether the data packet includes at least one of: a start of frame field; a control word; an address field; a data field; and an idle indicator.  
     
     
         23 . The apparatus of  claim 13  wherein the control word includes at least one of: a command to be performed; and the random access memory device to perform the command.  
     
     
         24 - 66 . (Cancelled)