Method and apparatus for verifying error correcting codes

Abstract

A method and an apparatus verifies the correctness of the error correcting code algorithm and the correctness of the error correcting code implementation. An error injection module is used to inject random errors into an ECC circuit between an encoder and a decoder. The encoder encodes data bits with check bits to produce an encoded signal. A decoder decodes the encoded signal, after modification by the error injection module. The output of the decoder may be a zero error signal, a signal error signal, a multiple error signal, and an error location signal. The output signal is compared to expected values to determine if an error exists in the ECC or the ECC circuit.

1 - 11 . (cancelled).  
     
     
         12 . A method for verifying an error correcting code (ECC) operating on an ECC circuit, comprising: 
 providing a data input signal to a data encoder;    generating an ECC encoded data signal comprising data bits and check bits;    on a random basis, injecting one of a single error signal and a multiple error signal into the ECC encoded data signal, and passing the ECC encoded data signal to indicate a no error condition, thereby producing; and an output signal; and    decoding the output signal to produce one or more decoded output signals indicative of one of the no error condition, a single error condition and a multiple error condition.    
     
     
         13 - 15 . (cancelled).  
     
     
         16 . The method of  claim 12 , further comprising; 
 comparing the one or more decoded output signals with corresponding expected signals; and    if the one or more decoded output signals and the corresponding expected signals do not match, declaring an error in the ECC or the ECC circuit.    
     
     
         17 . The method of  claim 12 , wherein the verification is a formal verification.  
     
     
         18 . The method of  claim 12 , wherein the method is executed on a simulation.  
     
     
         19 . The method of  claim 12 , wherein the decoded output signals comprise an error location signal.