Design method for semiconductor integrated circuit device

Abstract

A design method for a semiconductor integrated circuit device enabling flexible selection of IPs while securing the functions of a system is provided. The design method of the present invention includes the steps of: (a) storing a plurality of IPs having the same function in a memory for each of a plurality of functions; (b) constructing a function group structure for satisfying a certain specification; and (c) selecting and retrieving one IP from the plurality of IPs having the same function from the memory for each function in the function group structure and substituting the IP for the function in the function group structure.

What is claimed is:  
     
         1 . A design method for a semiconductor integrated circuit device comprising the steps of: 
 (a) storing a plurality of IPs having the same function in a memory for each of a plurality of functions;    (b) constructing a function group structure for satisfying a certain specification; and    (c) selecting and retrieving one IP from the plurality of IPs having the same function from the memory for each function in the function group structure and substituting the IP for the function in the function group structure.    
     
     
         2 . The design method of  claim 1 , further comprising the step of: 
 (e) mapping each function to a HW model and a SW model of architecture models in a database.    
     
     
         3 . The design method of  claim 2 , further comprising the step of: 
 (d) expanding the IP hierarchically into functional blocks after the step (c),    wherein in the step (e), each of the functional blocks obtained by the expansion is mapped to a HW model and a SW model of architecture models.    
     
     
         4 . A design method for a semiconductor integrated circuit device comprising the steps of: 
 (a) storing a plurality of IPs each having a function in a memory;    (b) constructing a function group structure for satisfying a certain specification;    (c) selecting and retrieving an IP having a function from the memory for each function in the function group structure and substituting the IP for the function in the function group structure;    (d) expanding the IP hierarchically into functional blocks; and    (e) mapping each of the functional blocks obtained by the hierarchical expansion to a HW model and a SW model of architecture models in a database.    
     
     
         5 . The design method of  claim 4 , wherein in the step (e), static analysis considering overlap of an area is performed for HW portions of the functional blocks.  
     
     
         6 . The design method of  claim 4 , further comprising the step of: 
 (f) performing dynamic performance analysis for determining the mapping of each functional block in the function group structure to a HW model and a SW model after the step (e).    
     
     
         7 . The design method of  claim 6 , wherein the database stores a SW model having a function equivalent to a HW model for each function of the HW model.  
     
     
         8 . The design method of  claim 7 , wherein in the step (f), the mapping of each functional block to a HW model and a SW model is switched so that the power consumption is kept from exceeding an upper limit.  
     
     
         9 . The design method of  claim 6 , wherein in the step (f), when the load rate of CPU obtained when a functional block is mapped to a HW model is below a certain lower limit, the mapping of the functional block is switched to a SW model.  
     
     
         10 . The design method of  claim 4 , wherein in the step (e), analysis considering power consumption of a memory is performed.  
     
     
         11 . A design method for a semiconductor integrated circuit device comprising the steps of: 
 (a) storing a plurality of HW models in a memory as architecture models; and    (b) retrieving architecture models from the memory to construct an architecture group structure satisfying a certain specification,    wherein in the step (b), the architecture group structure is constructed so that the architecture group structure includes a plurality of bus models and a plurality of bus bridge models for connecting the bus models.    
     
     
         12 . The design method of  claim 11 , wherein in the step (b), the bus bridge model connects two bus models having different widths in a manner of adjusting the bus widths and the data transfer speeds.  
     
     
         13 . A design method for a semiconductor integrated circuit device comprising the steps of: 
 (a) storing a plurality of HW models in a memory as architecture models;    (b) retrieving architecture models from the memory to construct an architecture group structure satisfying a certain specification,    (c) constructing a function group structure for satisfying the certain specification;    (d) providing test benches on input and output sides of the function group structure; and    (e) mapping functions in the function group structure and the test benches to the models in the architecture group structure.    
     
     
         14 . The design method of  claim 13 , wherein in the step (a), the plurality of models include an I/F model, and 
 in the step (b), the architecture group structure is constructed so as to include an I/F model.    
     
     
         15 . The design method of  claim 14 , wherein in the step (e), the test bench on the input or output side is mapped to the I/F model in the architecture group structure.  
     
     
         16 . The design method of  claim 13 , wherein in the step (a), the plurality of architecture models include a memory model, 
 in the step (b), the architecture group structure is constructed so as to include a memory model in the architecture group structure, and    in the step (e), the test bench on the input or output side is mapped to the memory model in the architecture group structure.    
     
     
         17 . A design method for a semiconductor integrated circuit device comprising the steps of: 
 (a) storing a plurality of IPs each having a function in a memory;    (b) constructing a function group structure for satisfying a certain specification;    (c) selecting and retrieving an IP having a function from the memory for each function in the function group structure, and substituting the IP for the function in the function group structure;    (d) expanding the IP hierarchically to functional blocks;    (e) mapping each functional block obtained by the hierarchical expansion to a model in an architecture group structure; and    (f) preparing an inter-block connection table describing a path from the functional block to another functional block receiving an output from the functional block as an intermodel path in the architecture models.    
     
     
         18 . A design method for a semiconductor integrated circuit device comprising the steps of: 
 (a) storing a plurality of IPs each having a function in a memory;    (b) constructing a function group structure for satisfying a certain specification;    (c) selecting and retrieving an IP having a function from the memory for each function in the function group structure and substituting the IP for the function in the lo function group structure;    (e) mapping each function in the function group structure to a model in architecture models in a database;    (f) setting priority of the model for access to a bus; and    (g) performing static performance analysis for the function group structure in the state where the respective functions in the function group structure have been mapped to the models,    wherein in the static performance analysis, the power consumption of the function group structure is calculated using the priority of each model for access to a bus in the architecture group structure instead of the number of toggles.