Graphics accelerator

Abstract

A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.

1 . A graphics accelerator comprising: 
 a memory for graphics data, the graphics data including pixels; and    a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data.    
     
     
         2 . The graphics accelerator of  claim 1  wherein the memory includes a data SRAM.  
     
     
         3 . The graphics accelerator of  claim 1  further comprising a direct memory access (DMA) engine for loading the graphics data from memory through loading operations and transferring processed graphics data to the memory through storing operations.  
     
     
         4 . The graphics accelerator of  claim 1  wherein the coprocessor processes the plurality of components of each pixel in parallel as three elements of a vector.  
     
     
         5 . The graphics accelerator of  claim 4  wherein the plurality of components of each pixel comprise R, G and B components of RGB formatted graphics data.  
     
     
         6 . The graphics accelerator of  claim 5  wherein the pixels are in an RGB16 format.  
     
     
         7 . The graphics accelerator of  claim 6  wherein the R component has five bits, the G component has six bits and the B component has 5 bits.  
     
     
         8 . The graphics accelerator of  claim 6  wherein the graphics data is organized into 32-bit words, and each 32-bit word includes two pixels having RGB16 format.  
     
     
         9 . The graphics accelerator of  claim 8  wherein the two pixels are respectively selected by two special load instructions.  
     
     
         10 . The graphics accelerator of  claim 9  wherein the two special load instructions are for loading a left one and a right one of the two pixels, respectively.  
     
     
         11 . The graphics accelerator of  claim 7  wherein the coprocessor comprises an input register.  
     
     
         12 . The graphics accelerator of  claim 11  wherein the R, G and B components are expanded into 8-bit components through zero expansion when loaded into the input register.  
     
     
         13 . The graphics accelerator of  claim 4  wherein the plurality of components of each pixel comprise Y, U and V components of YUV formatted graphics data, and 
 wherein the Y, U and V components are also referred to as Y, Cr and Cb components, respectively, of YCrCb formatted graphics data.  
 
     
     
         14 . The graphics accelerator of  claim 13  wherein the pixels are in a YUV 4:2:2 format.  
     
     
         15 . The graphics accelerator of  claim 14  wherein the pixels are organized into 32-bit words and each 32-bit word contains two pixels.  
     
     
         16 . The graphics accelerator of  claim 15  wherein the two pixels in each 32-bit word is organized in a YUYV format, each of the first Y component, the U component, the second Y component, and the V component occupies eight bits, a first one of the two pixels is comprised of a first Y component, the U component and the V component, and a second one of the two pixels is comprised of the second Y component, the U component and the V component.  
     
     
         17 . The graphics accelerator of  claim 15  wherein the two pixels are respectively selected by two special load instructions.  
     
     
         18 . The graphics accelerator of  claim 17  wherein the two special load instructions are for extracting a first one and a second one of the two pixels, respectively.  
     
     
         19 . The graphics accelerator of  claim 4  wherein the coprocessor has an instruction set that includes a special instruction for comparing between each element of a pair of 3-element vectors.  
     
     
         20 . The graphics accelerator of  claim 19  wherein the coprocessor further comprises a result register, and results of the three comparisons are stored in the result register.  
     
     
         21 . The graphics accelerator of  claim 20  wherein the results of the three comparisons are used together during a single conditional branch operation.  
     
     
         22 . The graphics accelerator of  claim 19  wherein the special instruction is for a greater-than-or-equal-to operation.  
     
     
         23 . The graphics accelerator of  claim 3  wherein the DMA engine moves data between the memory and an external memory at the same time the graphics accelerator is using the memory for its load and store operations.  
     
     
         24 . The graphics accelerator of  claim 23  wherein the external memory is a unified memory that is shared by a graphics display system, a CPU and other peripheral devices.  
     
     
         25 . The graphics accelerator of  claim 3  wherein the DMA engine includes a queue to hold a plurality of DMA commands.  
     
     
         26 . The graphics accelerator of  claim 25  wherein the plurality of DMA commands are executed in the order they are received.  
     
     
         27 . The graphics accelerator of  claim 25  wherein the queue comprises a mechanism that allows the graphics accelerator to determine when all the DMA commands have been completed.  
     
     
         28 . The graphics accelerator of  claim 25  wherein the queue is four deep for storing up to four DMA commands.  
     
     
         29 . The graphics accelerator of  claim 3  wherein the graphics accelerator is working on operands and producing outputs for one set of pixels, while the DMA engine is bringing in operands for a future set of pixel operations.  
     
     
         30 . A method of processing graphics comprising the steps of: 
 loading graphics data into a graphics accelerator having a coprocessor, the graphics data including pixels, each pixel having a plurality of components; and    performing vector type operations on the plurality of components of each pixel of graphics data using the coprocessor.    
     
     
         31 . The method of processing graphics of  claim 30  wherein the plurality of components comprises R, G and B components of RGB formatted graphics data.  
     
     
         32 . The method of processing graphics of  claim 31  wherein the pixels of the graphics data are in an RGB16 format.  
     
     
         33 . The method of processing graphics of claim 32 further comprising the step of organizing the graphics data into 32-bit words, wherein each 32-bit word includes two pixels having RGB16 format.  
     
     
         34 . The method of processing graphics of  claim 33  further comprising the step of selecting each of the two pixels with one of two special load instructions.  
     
     
         35 . The method of processing graphics of  claim 34  wherein the step of selecting each of the two pixels comprises loading a left one of the two pixels.  
     
     
         36 . The method of processing graphics of  claim 34  wherein the step of selecting each of the two pixels comprises loading a right one of the two pixels.  
     
     
         37 . The method of processing graphics of  claim 30  wherein each of the plurality of pixels of graphics data comprises Y, U and V components of YUV formatted graphics data.  
     
     
         38 . The method of processing graphics of  claim 37  wherein the pixels are in a YUV 4:2:2 format.  
     
     
         39 . The method of processing graphics of  claim 38  further comprising the step of organizing the pixels into 32-bit words, wherein each 32-bit word contains two pixels.  
     
     
         40 . The method of processing graphics of  claim 39  wherein the step of organizing the pixels into 32-bit words comprises organizing each of the two pixels into a YUYV format, wherein each of the first Y component, the U component, the second Y component and the V component occupies eight bits, a first one of the two pixels is comprised of a first Y component, the U component and the V component, and a second one of the two pixels is comprised of the second Y component, the U component and the V component.  
     
     
         41 . The method of processing graphics of  claim 40  further comprising the step of selecting each of the two pixels with one of two special load instructions.  
     
     
         42 . The method of processing graphics of  claim 41  wherein the step of selecting each of the two pixels comprises loading the first one of the two pixels.  
     
     
         43 . The method of processing graphics of  claim 42  wherein the step of selecting each of the two pixels comprises loading the second one of the two pixels.  
     
     
         44 . The method of processing graphics of  claim 30  further comprising the step of comparing between each element of a pair of 3-element vectors, wherein each element of the 3-element vector is one of three components of each pixel.  
     
     
         45 . The method of processing graphics of  claim 44  wherein the three components of each pixel are R, G and B components.  
     
     
         46 . The method of processing graphics of  claim 44  wherein the three components of each pixel are Y, U and V components.  
     
     
         47 . The method of processing graphics of  claim 44  wherein the coprocessor includes a result register, and the method further comprising the step of storing results of the three comparisons in the result register.  
     
     
         48 . The method of processing graphics of  claim 47  further comprising the step of performing a single conditional branch operation using the results of the three comparisons.  
     
     
         49 . The method of processing graphics of  claim 44  wherein the step of comparing between each element of a pair of 3-element vectors comprises the step of performing a greater-than-or-equal-to operation between each element of a pair of 3-element vectors.  
     
     
         50 . The method of processing graphics of  claim 30  wherein the graphics accelerator includes a memory for loading the graphics data further comprising the step of moving data between the memory and an external memory using a direct memory access (DMA) engine at the same time the graphics accelerator is using the memory for its load and store operations.  
     
     
         51 . The method of processing graphics of  claim 50  wherein the memory is a data SRAM.  
     
     
         52 . The method of processing graphics of  claim 50  wherein the external memory is a unified memory that is shared by a graphics display system, a CPU and other peripheral devices.  
     
     
         53 . The method of processing graphics of  claim 50  wherein the DMA engine includes a queue for holding a plurality of DMA commands.  
     
     
         54 . The method of processing graphics of  claim 53  further comprising the step of determining whether all the DMA commands have been completed.  
     
     
         55 . The method of processing graphics of  claim 53  further comprising the step of receiving the plurality of DMA commands.  
     
     
         56 . The method of processing graphics of  claim 55  further comprising the step of executing the plurality of DMA commands in the order they are received.  
     
     
         57 . The method of processing graphics of  claim 53  wherein the queue is four deep for storing up to four DMA commands.  
     
     
         58 . The method of processing graphics of  claim 30  further comprising the step of bringing in operands for a future set of pixel operations using a direct memory access (DMA) engine while the graphics accelerator is working on operands and producing outputs for one set of pixels.