US2004257861A1PendingUtilityA1
Method of incorporating magnetic materials in a semiconductor manufacturing process
Priority: Jun 17, 2003Filed: Jun 17, 2003Published: Dec 23, 2004
Est. expiryJun 17, 2023(expired)· nominal 20-yr term from priority
G11C 11/14H01F 41/32B82Y 10/00H01F 10/30H10B 61/00
34
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Claims
Abstract
A method for incorporating magnetic materials in a semiconductor manufacturing process includes manufacturing a semiconductor device including interlayers and dielectric layers, depositing a magnetic layer above a semiconductor device and forming metallized contacts for connecting interlayers of the semiconductor device. With the method of the present invention, the deposition of the magnetic material is integrated with the semiconductor manufacturing process.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method for incorporating magnetic elements in a semiconductor manufacturing process, wherein the semiconductor manufacturing process comprises steps for manufacturing semiconductor devices, comprising:
manufacturing the semiconductor devices; forming a layer of magnetic material above the semiconductor devices after the semiconductor devices are formed; patterning and etching the layer of magnetic material to form magnetic elements; depositing a dielectric layer on a top surface of the magnetic elements; and forming via holes and contacts through the dielectric layer to contact the semiconductor device.
2 . The method of claim 1 , further comprising, before forming magnetic elements, depositing a dielectric underlayer on top of the semiconductor devices; and depositing a silicon nitride (Si 3 N 4 ) seed layer on top of the dielectric underlayer.
3 . The method of claim 2 , wherein the dielectricd underlayer comprises a structure of TEOS/SOG/BSPG, wherein the thickness of the dielectric underlayer is about 4000 Å and the thickness of the seed layer is about 1000 Å.
4 . The method of claim 1 , wherein the step of patterning the magnetic layer to form the magnetic elements comprises:
depositing a silicon nitride layer on top of the layer of magnetic material; etching off portions of the silicon nitride layer in a first etching process; etching the layer of magnetic material in a second etching process which uses remaining silicon nitride which was not etched off in the first etching process as a mask to form the magnetic elements.
5 . The method of claim 4 , wherein the magnetic material is CoFe with a ratio of Co to Fe of 0.9:0.1.
6 . The method of claim 4 , wherein the magnetic material has a coercive field of 10-70 Oe.
7 . The method of claim 4 , wherein the layer of magnetic material has a thickness of about 600 Å and the silicon nitride layer has a thickness of about 2800 Å.
8 . The method of claim 4 , further comprising depositing a CrSi layer before depositing the silicon nitride layer.
9 . The method of claim 8 , wherein the CrSi layer has a thickness of about 200 Å.
10 . The method of claim 1 , wherein the dielectric layer comprises a structure of TEOS/TEOS and has a thickness of about 4000 Å.
11 . The method of claim 1 , wherein the magnetic dielectric layer comprises a structure of TEOS/SOG/TEOS and has a thickness of about 4000 Å.
12 . The method of claim 1 , wherein the semiconductor devices are one of CMOS devices and bipolar transistors.
13 . A magnetoelectronic semiconductor device, comprising:
semiconductor devices each comprising a gate, a drain and source; a magnetic element formed above the semiconductor device; a dielectric layer formed on top of the magnetic element; and metallized contacts penetrating through the dielectric layer to contact with the semiconductor device.
14 . The magnetoelectronic device of claim 13 , wherein the magnetic element comprises CoFe and the ratio of Co to Fe is 0.9:0.1.
15 . The magnetoelectronic of claim 13 , wherein the magnetic element has a coercive field of 10-70 Oe.
16 . The magnoelectronic device of claim 13 , wherein the semiconductor device is CMOS.
17 . A magnetoelectronic device, comprising:
a semiconductor device manufactured by a semiconductor manufacturing process, wherein the semiconductor comprises a gate, drain and source; a Hall sensor formed in associated with the semiconductor device; and a magnetic element which is deposited on top of the semiconductor device; wherein the Hall sensor and magnetic element are formed integrally with the manufacturing process of the semiconductor device; and wherein the magnetic element is formed above the Hall sensor, with a distance sufficiently close to the Hall sensor such that a magnetic flux from the magnetic material can reach and be detected by the Hall sensor.
18 . The magnetoelectronic device of claim 17 , further comprising a dielectric layer above the magnetic element and metallized contacts penetrating through the dielectric layer to contact the semiconductor device.
19 . The magnetoelectronic device of claim 17 , wherein the magnetic element are patterned and positioned with respect to the Hall sensor such that the external magnetic field reaching the sensor is amplified several times.
20 . The magnetoelectronic device of claim 17 , wherein the magnetic material is permalloy.
21 . The magnetoelectronic device of claim 17 , wherein the magnetic material has a coersivity of 0.01 Oe.
22 . The magnetoelectronic device of claim 17 , wherein the magnetic material comprises CoFe and the ratio of Co to Fe is 0.9:0.1.
23 . The magnetoelectronic device of claim 22 , wherein magnetic material has a coersive field in a range of 10-70 Oe.
24 . The magnetoelectronic device of claim 17 , wherein the semiconductor device is CMOS.
25 . The magnetoelectronic device of claim 17 , wherein the semiconductor device is a CMOS device and is formed on a SOI (spin-on-isolation) material.Cited by (0)
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