Information processing device and peripheral devices used therewith

Abstract

An information processing device such as a game machine is selectively connectable to different peripheral devices such as memory devices. The peripheral devices may be provided with characteristics for distinguishing one from another. The information processing device carries out operations based on the peripheral device connected thereto The information processing device may also access memories which store data having different data widths.

1 . An information processing device which is detachably connectable to different peripheral devices each using a different data width, wherein at least one of the peripheral devices is provided with a characteristic for distinguishing that peripheral device from other peripheral devices, the information processing device comprising: 
 a detecting circuit for detecting, based on the characteristic, which of the peripheral devices is connected to the information processing device;    a processor for sending and/or receiving data via a data bus to/from the connected peripheral device; and    bus control circuitry for selectively controlling the data bus in accordance with one of a plurality of different bus control modes based on which of the peripheral devices is detected by the detecting circuit.    
     
     
         2 . An information processing device as described in  claim 1 , wherein the different peripheral devices include at least two different memory devices.  
     
     
         3 . An information processing device as described in  claim 2 , wherein each of the at least two different devices includes a memory storing a game program.  
     
     
         4 . An information processing device as described in  claim 1 , wherein the detecting circuit comprises a shape detecting circuit.  
     
     
         5 . An information processing device as described in  claim 1 , wherein the information processing device comprises a game machine.  
     
     
         6 . An information processing device as described in  claim 1 , wherein the information processing device comprises a hand-held game machine.  
     
     
         7 . An information processing device as described in  claim 1 , wherein the plurality of bus control modes comprise a normal bus transfer mode and a multiplex bus transfer mode.  
     
     
         8 . A peripheral device detachably connectable with an information processing device via a connector to a bus having a first data width, the peripheral device comprising: 
 an electrical component which uses a second data width wider than said first data width; and    a multiplex bus conversion circuit for controlling, in a time-sharing manner, address and data exchange between the bus of the information processing device having the first data width and the electrical component using the second data width.    
     
     
         9 . A peripheral device as described in  claim 8 , wherein the multiplex bus conversion circuit comprises an address counter.  
     
     
         10 . A peripheral device as described in  claim 8 , wherein the electrical component comprises a general purpose memory.  
     
     
         11 . A peripheral device according to  claim 8 , wherein the multiplex bus conversion circuit comprises: 
 an address storing circuit for storing an address value supplied from the information processing device via the bus; and    an increment circuit for periodically incrementing the address value stored in the address storing circuit in response to a control signal supplied from the information processing device via the bus.    
     
     
         12 . A memory device detachably connectable with a game machine via a connector to a bus having a first data width, the memory device comprising: 
 a first memory which uses a second data width wider than said first data width; and    a multiplex bus conversion circuit for controlling, in a time-sharing manner, address and data exchange between the bus of the information processing device having the first data width and the first memory using the second data width.    
     
     
         13 . A memory device as described in  claim 12 , further comprising: 
 a second memory which uses the first data width.    
     
     
         14 . A peripheral device according to  claim 12 , wherein the multiplex bus conversion circuit comprises: 
 an address storing circuit for storing an address value supplied from the game machine via the bus; and    an increment circuit for periodically incrementing the address value stored in the address storing circuit in response to a control signal supplied from the game machine via the bus.    
     
     
         15 . A memory access method for a hand-held display system for playing video games which includes user controls, a liquid crystal display and a processor, the method comprising: 
 accessing by the processor a first portion of a memory which stores data having a first data width using a multiplex memory accessing scheme; and    accessing by the processor of a second portion of the memory which stores data having a second data width using a non-multiplex accessing scheme.    
     
     
         16 . The memory access method according to  claim 15 , wherein the first portion of the memory comprises a read-only memory portion and the second portion of the memory comprises a read/write memory portion.  
     
     
         17 . The memory access method according to  claim 16 , wherein the read-only memory portion stores a video game program.  
     
     
         18 . The memory access method according to  claim 15 , wherein the first portion of the memory comprises a read-only portion addressable using addresses in an address range from 08000000h to 0DFFFFFFh and the second portion of the memory comprises a read/write portion addressable using addresses in an address range from 0E000000h to 0E00FFFFh.  
     
     
         19 . The memory access method according to  claim 15 , wherein the first portion of the memory comprises a 16-bit memory portion that is addressable using a 24-bit address and the second portion of the memory comprises an 8-bit memory that is addressable using a 16-bit address.  
     
     
         20 . The memory access method according to  claim 15 , wherein the multiplex memory accessing scheme selectively provides for sequential access and random access of the first portion of the memory.  
     
     
         21 . A bus control method for a hand-held display system for playing video games which includes user controls, a liquid crystal display and a processor, the method comprising: 
 controlling a bus using a multiplex bus control method when accessing a first portion of a memory which stores data having a first data width; and    controlling a bus using a non-multiplex bus control method when accessing a second portion of the memory which stores data having a second data width.    
     
     
         22 . A hand-held display system for playing video games, comprising: 
 user controls;    a display; and    a processor for accessing a first portion of a memory which stores data having a first data width using a multiplex memory accessing scheme and for accessing a second portion of the memory which stores data having a second data width using a non-multiplex accessing scheme.    
     
     
         23 . The hand-held display system according to  claim 22 , wherein the first portion of the memory comprises a read-only memory portion and the second portion of the memory comprises a read/write memory portion.  
     
     
         24 . The hand-held display system according to  claim 23 , wherein the read-only memory portion stores a video game program.  
     
     
         25 . The hand-held display system according to  claim 22 , wherein the first portion of the memory comprises a read-only portion addressable using addresses in an address range from 08000000h to 0DFFFFFFh and the second portion of the memory comprises a read/write portion addressable using addresses in an address range from 0E000000h to 0E00FFFFh.  
     
     
         26 . The hand-held display system according to  claim 22 , wherein the first portion of the memory comprises a 16-bit memory portion that is addressable using a 24-bit address and the second portion of the memory comprises an 8-bit memory that is addressable using a 16-bit address.  
     
     
         27 . The hand-held display system according to  claim 22 , wherein the multiplex memory accessing scheme selectively provides for sequential access and random access of the first portion of the memory.