High performance silicon condenser microphone with perforated single crystal silicon backplate

Abstract

A silicon condenser microphone is described. The silicon condenser microphone of the present invention comprises a perforated backplate comprising a portion of a single crystal silicon substrate, a support structure formed on the single crystal silicon substrate, and a floating silicon diaphragm supported at its edge by the support structure and lying parallel to the perforated backplate and separated from the perforated backplate by an air gap.

1 . A method of fabricating a perforated silicon diaphragm comprising: 
 providing a single crystal silicon substrate of a first conductivity type;    blanket implanting first ions of a second conductivity type opposite said first conductivity type into said single crystal silicon substrate to form an etch stop layer;    selectively implanting second ions of said first conductivity type into said single crystal silicon substrate to form a pattern of holes in a portion of said substrate;    implanting third ions of said first conductivity type overlying said pattern of holes and forming a first ohmic contact region;    implanting fourth ions of said second conductivity type not surrounding said pattern of holes to form a second ohmic contact region;    thereafter depositing a nitride layer on a frontside and a backside of said silicon substrate;    forming contacts through said nitride layer to said first and second ohmic contact regions;    thereafter patterning said backside nitride layer; and    from the backside, etching away said silicon substrate not covered by said nitride layer to said etch stop layer and simultaneously selectively etching away said pattern of holes to complete formation of said perforated diaphragm.    
   
   
       2 . The method according to  claim 1  wherein said first conductivity type is P-type and wherein said second conductivity type is N-type.  
   
   
       3 . The method according to  claim 1  wherein said first ions are N− ions, said second ions are P+ ions, said third ions are P++ ions, and said fourth ions are N++ ions.  
   
   
       4 . The method according to  claim 1  wherein said nitride layer is deposited by low pressure chemical vapor deposition.  
   
   
       5 . The method according to  claim 1  wherein said nitride layer has a thickness of between about 1000 and 1500 Angstroms.  
   
   
       6 . The method according to  claim 1  wherein said etch stop layer has a depth into said silicon substrate of between about 1 and 10 microns.  
   
   
       7 . The method according to  claim 1  wherein said step of forming contacts through said nitride layer to said first and second ohmic contact regions comprises: 
 etching contact openings through said nitride layer to said first and second ohmic contact regions;    depositing a metal layer within said contact openings and overlying said nitride layer; and    patterning said metal layer to form a first electrode contacting said first ohmic contact region and a second electrode contacting said second ohmic contact region.    
   
   
       8 . The method according to  claim 1  wherein said step of etching away said silicon substrate not covered by said nitride layer to said etch stop layer and simultaneously selectively etching away said pattern of holes comprises KOH with a 4 electrode electrochemical etching (ECE) configuration.  
   
   
       9 . A method of fabricating a perforated silicon diaphragm comprising: 
 providing a single crystal silicon substrate of a first conductivity type;    blanket implanting first ions of a second conductivity type opposite said first conductivity type into said single crystal silicon substrate to form an etch stop layer wherein a depth of said etch stop layer into said silicon substrate determines a thickness of said perforated diaphragm;    selectively implanting second ions of said first conductivity type into said single crystal silicon substrate to form a pattern of holes in a portion of said substrate;    implanting third ions of said first conductivity type overlying said pattern of holes and forming a first ohmic contact region;    implanting fourth ions of said second conductivity type not surrounding said pattern of holes to form a second ohmic contact region;    thereafter depositing a nitride layer on a frontside and a backside of said silicon substrate;    forming contacts through said nitride layer to said first and second ohmic contact regions;    thereafter patterning said backside nitride layer; and    from the backside, etching away said silicon substrate not covered by said nitride layer to said etch stop layer and simultaneously selectively etching away said pattern of holes to complete formation of said perforated diaphragm.    
   
   
       10 . The method according to  claim 9  wherein said first conductivity type is P-type and wherein said second conductivity type is N-type.  
   
   
       11 . The method according to  claim 9  wherein said first ions are N− ions, said second ions are P+ ions, said third ions are P++ ions, and said fourth ions are N++ ions.  
   
   
       12 . The method according to  claim 9  wherein said nitride layer is deposited by low pressure chemical vapor deposition.  
   
   
       13 . The method according to  claim 9  wherein said nitride layer has a thickness of between about 1000 and 1500 Angstroms.  
   
   
       14 . The method according to  claim 9  wherein said etch stop layer has a depth into said silicon substrate of between about 1 and 10 microns.  
   
   
       15 . The method according to  claim 9  wherein said step of forming contacts through said nitride layer to said first and second ohmic contact regions comprises: 
 etching contact openings through said nitride layer to said first and second ohmic contact regions;    depositing a metal layer within said contact openings and overlying said nitride layer; and    patterning said metal layer to form a first electrode contacting said first ohmic contact region and a second electrode contacting said second ohmic contact region.    
   
   
       16 . The method according to  claim 9  wherein said step of etching away said silicon substrate not covered by said nitride layer to said etch stop layer and simultaneously selectively etching away said pattern of holes comprises KOH with a 4 electrode electrochemical etching (ECE) configuration.  
   
   
       17 . A method of fabricating a perforated silicon diaphragm comprising: 
 providing a single crystal silicon substrate of a first conductivity type; 
 blanket implanting at a first dose first ions of a second conductivity type opposite said first conductivity type into said single crystal silicon substrate to form an etch stop layer wherein a depth of said etch stop layer into said silicon substrate determines a thickness of said perforated diaphragm;  
 selectively implanting at a second dose second ions of said first conductivity type into said single crystal silicon substrate to form a pattern of holes in a portion of said substrate;  
 implanting at a third dose third ions of said first conductivity type overlying said pattern of holes and forming a first ohmic contact region;  
 implanting at a fourth dose fourth ions of said second conductivity type not surrounding said pattern of holes to form a second ohmic contact region;  
 thereafter depositing a nitride layer on a frontside and a backside of said silicon substrate;  
 forming contacts through said nitride layer to said first and second ohmic contact regions;  
 thereafter patterning said backside nitride layer; and  
 from the backside, etching away said silicon substrate not covered by said nitride layer to said etch stop layer and simultaneously selectively etching away said pattern of holes to complete formation of said perforated diaphragm.  
   
   
   
       18 . The method according to  claim 17  wherein said first dose is lower than the second, third, and fourth doses.  
   
   
       19 . The method according to  claim 17  wherein said first conductivity type is P-type and wherein said second conductivity type is N-type.  
   
   
       20 . The method according to  claim 17  wherein said first ions are N− ions, said second ions are P+ ions, said third ions are P++ ions, and said fourth ions are N++ ions.  
   
   
       21 . The method according to  claim 17  wherein all of said steps up to said patterning said backside nitride layer step can be CMOS compatible processes.  
   
   
       22 . The method according to  claim 17  wherein, said etch stop layer has a depth into said silicon substrate of between about 1 and 10 microns.  
   
   
       23 . The method according to  claim 17  wherein said step of forming contacts through said nitride layer to said first and second ohmic contact regions comprises: 
 etching contact openings through said nitride layer to said first and second ohmic contact regions;    depositing a metal layer within said contact openings and overlying said nitride layer; and    patterning said metal layer to form a first electrode contacting said first ohmic contact region and a second electrode contacting said second ohmic contact region.    
   
   
       24 . The method according to  claim 17  wherein said step of etching away said silicon substrate not covered by said nitride layer to said etch stop layer and simultaneously selectively etching away said pattern of holes corn with a 4 electrode electrochemical etching (ECE) configuration.  
   
   
       25 . The method according to  claim 23  wherein said step of implanting at a third dose third ions of said first conductivity type overlying said pattern of holes connects said pattern of holes together to provide external electric biases for said ECE configuration.