Low jitter external clocking

Abstract

A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.

1 - 4 . (Canceled)  
   
   
       5 . A semiconductor die comprising: 
 a first clock signal line and a second clock signal line to receive a differential clock signal;    a first differential amplifier coupled to the first clock signal line and the second clock signal line to amplify the differential clock signal into a first single-ended clock signal;    a second differential amplifier coupled to the first clock signal line and the second clock signal line to amplify the differential clock signal into a second single-ended clock signal;    an inverter having an input coupled to the first differential amplifier to receive the first single-ended clock signal and to invert the first single-ended clock signal at an output; and    a voltage follower having an input coupled to the second differential amplifier to receive the second single-ended clock signal and an output connected to the output of the inverter to generate a single-ended output clock signal.    
   
   
       6 . The semiconductor die of  claim 5  wherein: 
 the first differential amplifier further comprises a non-inverting input coupled to the first clock signal line and an inverting input coupled to the second clock signal line;    the second differential amplifier further comprises an inverting input coupled to the first clock signal line and a non-inverting input coupled to the second clock signal line;    the inverter comprises: 
 a p-channel transistor coupled between a voltage supply and an output line and having a control terminal coupled to the first differential amplifier to receive the first single-ended clock signal; and  
 an n-channel transistor coupled between the output line and a voltage reference and having a control terminal coupled to the first differential amplifier to receive the first single-ended ended clock signal; and  
   the voltage follower comprises: 
 an n-channel transistor coupled between the voltage supply and the output line and having a control terminal coupled to the second differential amplifier to receive the second single-ended clock signal; and  
 a p-channel transistor coupled between the output line and the voltage reference and having a control terminal coupled to the second differential amplifier to receive the second single-ended clock signal.  
   
   
   
       7 . The semiconductor die of  claim 6 , further comprising: 
 a buffer circuit coupled to the output line to buffer the single-ended output clock signal; and    a biasing circuit to bias the first differential amplifier and the second differential amplifier.    
   
   
       8 . A system comprising: 
 a first circuit;    a second circuit;    a communication link coupled between the first circuit and the second circuit, the communication link comprising: 
 a data bus; and  
 a first clock signal line and a second clock signal line coupled to receive a differential clock signal from the second circuit;  
   a receiver circuit in the first circuit comprising: 
 a first differential amplifier coupled to the first clock signal line and the second clock signal line to amplify the differential clock signal into a first single-ended clock signal;  
 a second differential amplifier coupled to the first clock signal line and the second clock signal line to amplify the differential clock signal into a second single-ended clock signal;  
 an inverter having an input coupled to the first differential amplifier to receive the first single-ended clock signal and to invert the first single-ended clock signal at an output; and  
 a voltage follower having an input coupled to the second differential amplifier to receive the second single-ended clock signal and an output connected to the output of the inverter to generate a single-ended output clock signal.  
   
   
   
       9 . The system of  claim 8  wherein: 
 the first differential amplifier further comprises a non-inverting input coupled to the first clock signal line and an inverting input coupled to the second clock signal line;    the second differential amplifier further comprises an inverting input coupled to the first clock signal line and a non-inverting input coupled to the second clock signal line;    the inverter comprises: 
 a p-channel transistor coupled between a voltage supply and an output line and having a control terminal coupled to the first differential amplifier to receive the first single-ended clock signal; and  
 an n-channel transistor coupled between the output line and a voltage reference and having a control terminal coupled to the first differential amplifier to receive the first single-ended clock signal; and  
   the voltage follower comprises: 
 an n-channel transistor coupled between the voltage supply and the output line and having a control terminal coupled to the second differential amplifier to receive the second single-ended clock signal; and  
 a p-channel transistor coupled between the output line and the voltage reference and having a control terminal coupled to the second differential amplifier to receive the second single-ended clock signal.  
   
   
   
       10 . The system of  claim 9 , further comprising: 
 a buffer circuit coupled to the output line to buffer the single-ended output clock signal; and    a biasing circuit to bias the first differential amplifier and the second differential amplifier.    
   
   
       11 . The system of  claim 8  wherein the first circuit and the second circuit are located in a single semiconductor die.  
   
   
       12 . The system of  claim 8  wherein: 
 the first circuit is located in a first semiconductor die; and    the second circuit is located in a second semiconductor die.    
   
   
       13 . The system of  claim 8 , further comprising: 
 a plurality of circuits;    a very high frequency common clock generator coupled to each of the circuits to generate a very high frequency clock signal;    a plurality of communication links, each circuit being coupled to one or more neighboring circuits by one of the communication links, each communication link comprising: 
 a data bus;  
 a first differential clock signal line coupled to carry a very high frequency differential clock signal in a first direction; and  
 a second differential clock signal line coupled to carry a very high frequency differential clock signal in a second direction;  
   a differential clock signal generating circuit in each circuit coupled to one or more of the differential clock signal lines in one or more of the communication links to generate a very high frequency differential clock signal; and    a receiver circuit in each circuit to receive one of the very high frequency differential clock signals.    
   
   
       14 . The system of  claim 13  wherein each differential clock signal line comprises a first clock signal line and a second clock signal line to carry one of the very high frequency differential clock signals.  
   
   
       15 . The system of  claim 13  wherein each receiver circuit comprises: 
 a first differential amplifier coupled to one of the differential clock signal lines to amplify one of the very high frequency differential clock signals into a first single-ended clock signal;    a second differential amplifier coupled to the differential clock signal line to amplify the very high frequency differential clock signal into a second single-ended clock signal;    an inverter having an input coupled to the first differential amplifier to receive the first single-ended clock signal and to invert the first single-ended clock signal at an output; and    a voltage follower having an input coupled to the second differential amplifier to receive the second single-ended clock signal and an output connected to the output of the inverter to generate a single-ended output clock signal.    
   
   
       16 . The system of  claim 13  wherein the circuits are located in a single semiconductor die.  
   
   
       17 . The system of claim  1 . 3  wherein the circuits are located in two or more separate semiconductor dies.  
   
   
       18 - 21 . (Canceled)  
   
   
       22 . A method comprising: 
 receiving a differential clock signal on a first clock signal line and a second clock signal line;    amplifying the differential clock signal into a first single-ended clock signal in a first differential amplifier coupled to the first clock signal line and the second clock signal line;    amplifying the differential clock signal into a second single-ended clock signal in a second differential amplifier coupled to the first clock signal line and the second clock signal line;    inverting the first single-ended clock signal in an inverter to generate an inverted single-ended ended clock signal; and    combining the inverted single-ended clock signal with the second single-ended clock signal buffered by a voltage follower to generate a single-ended output clock signal.    
   
   
       23 . The method of  claim 22  wherein amplifying the differential clock signal into a second single-ended clock signal further comprises amplifying the differential clock signal into a second single-ended clock signal that is 180 degrees out of phase with the first single-ended clock signal.  
   
   
       24 . The method of  claim 22  wherein: 
 inverting the first single-ended clock signal in an inverter further comprises: 
 coupling the first single-ended clock signal to a gate of a p-channel transistor coupled between a voltage source and an output line; and  
 coupling the first single-ended clock signal to a gate of an n-channel transistor coupled between the output line and a voltage reference to generate the inverted single-ended clock signal on the output line; and  
   combining the inverted single-ended clock signal further comprises: 
 coupling the second single-ended clock signal to a gate of an n-channel transistor coupled between the voltage source and the output line; and  
 coupling the second single-ended clock signal to a gate of a p-channel transistor coupled between the output line and the voltage reference to generate the single-ended output clock signal on the output line.  
   
   
   
       25 . The method of  claim 22 , further comprising: 
 buffering the single-ended output clock signal; and    biasing the first differential amplifier and the second differential amplifier.    
   
   
       26 - 30 . (Canceled)  
   
   
       31 . The semiconductor die of  claim 5  wherein: 
 the semiconductor die further comprises a data line to receive a data signal; and    the differential clock signal is synchronized with the data signal.    
   
   
       32 . The system of  claim 8  wherein: 
 the data bus is coupled to receive a plurality of data signals from the second circuit; and    the differential clock signal is synchronized with the data signals.    
   
   
       33 . The system of  claim 8  wherein: 
 the first circuit or the second circuit comprises a microprocessor, a digital signal processor, a microcontroller, or an ASIC; and    the first circuit, the second circuit, and the communication link together comprise a video game, a hand-held calculator, a personal computer, a server, a workstation, a multi-processor computer system, a magnetic disk drive, a telecommunications modem, a routing switch, a cellular telephone, a pager, or a daily planner.    
   
   
       34 . The system of  claim 13  wherein: 
 one of the first circuit, the second circuit, or the plurality of circuits comprises a microprocessor, a digital signal processor, a microcontroller, or an ASIC; and    the first circuit, the second circuit, the plurality of circuits, the very high frequency common clock generator, and the communication links together comprise a video game, a hand-held calculator, a personal computer, a server, a workstation, a multi-processor computer system, a magnetic disk drive, a telecommunications modem, a routing switch, a cellular telephone, a pager, or a daily planner.    
   
   
       35 . The system of  claim 8  wherein: 
 the first circuit comprises a processor; and    the second circuit comprises a memory device or an input/output device.    
   
   
       36 . The system of  claim 8  wherein: 
 the first circuit comprises a processor;    the second circuit comprises a memory device comprising a random-access memory, a read-only memory, a cache memory, a hard disk drive, a floppy disk drive, an optical disk drive, or a tape cartridge drive; and    the system further comprises an input/output device comprising a monitor, a pointing device, a keyboard, or a modem coupled to the communication link.    
   
   
       37 . The method of  claim 22 , further comprising: 
 receiving a data signal on a data line; and    wherein the differential clock signal is synchronized with the data signal.    
   
   
       38 . A system comprising: 
 a magnetic disk drive; and    a semiconductor die coupled to the magnetic disk drive, the semiconductor die comprising: 
 a first clock signal line and a second clock signal line to receive a differential clock signal;  
 a first differential amplifier coupled to the first clock signal line and the second clock signal line to amplify the differential clock signal into a first single-ended clock signal;  
 a second differential amplifier coupled to the first clock signal line and the second clock signal line to amplify the differential clock signal into a second single-ended clock signal;  
 an inverter having an input coupled to the first differential amplifier to receive the first single-ended clock signal and to invert the first single-ended clock signal at an output connected to an output line; and  
 a voltage follower having an input coupled to the second differential amplifier to receive the second single-ended clock signal and an output connected to the output line to generate a single-ended output clock signal on the output line.  
   
   
   
       39 . The system of  claim 38  wherein: 
 the first differential amplifier further comprises a non-inverting input coupled to the first clock signal line and an inverting input coupled to the second clock signal line;    the second differential amplifier further comprises an inverting input coupled to the first clock signal line and a non-inverting input coupled to the second clock signal line;    the inverter comprises: 
 a p-channel transistor coupled between a voltage supply and the output line and having a control terminal coupled to the first differential amplifier to receive the first single-ended clock signal; and  
 an n-channel transistor coupled between the output line and a voltage reference and having a control terminal coupled to the first differential amplifier to receive the first single-ended clock signal; and  
   the voltage follower comprises: 
 an n-channel transistor coupled between the voltage supply and the output line and having a control terminal coupled to the second differential amplifier to receive the second single-ended clock signal; and  
 a p-channel transistor coupled between the output line and the voltage reference and having a control terminal coupled to the second differential amplifier to receive the second single-ended clock signal.  
   
   
   
       40 . The system of  claim 39 , further comprising: 
 a buffer circuit coupled to the output line to buffer the single-ended output clock signal; and    a biasing circuit to bias the first differential amplifier and the second differential amplifier.    
   
   
       41 . The system of  claim 38  wherein: 
 the semiconductor die further comprises a data line to receive a data signal; and    the differential clock signal is synchronized with the data signal.    
   
   
       42 . The system of  claim 38  wherein: 
 the semiconductor die comprises a processor; and    the magnetic disk drive is coupled to the processor through a data bus.